Fully digital AER convolution chip for vision processing

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 652-655

  Camuñas Mesa, Luis ^a   Acosta Jiménez, Antonio ^a   Serrano Gotarredona, Teresa ^a   Linares Barranco, Bernabé ^a  

^a UNIVERSITY OF SEVILLE   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL CONVOLUTION; INTERNATIONAL SYMPOSIUM; PROCESSING SYSTEMS; REAL TIME;

DIGITAL ARITHMETIC; FUNCTIONS; INTEGRATED CIRCUITS; PIXELS; TECHNICAL PRESENTATIONS;

CONVOLUTION;

EID: 51749124908     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541502     Document Type: Conference Paper

References (6)

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3. T. Serrano-Gotarredona, A. G. Andreou and B. Linares-Barranco, "AER image filtering architecture for vision processing systems", IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 9, pp. 1064-1071, Sep. 1999
4. R. Serrano-Gotarredona, T. Serrano-Gotarredona, A. Acosta-Jiménez and B. Linares-Barranco, "A Neuromorphic Cortical-Layer Microchip for Spike-Based Processing Vision Systems", in IEEE Transactions on Circuits and Systems, Part I, vol. 53, No. 12, pp. 2548-2564, December 2006
5. A. Linares-Barranco, G. Jimenez-Moreno, B. Linares-Barranco and A. Civit-Ballcels, "On algorithmic rate-coded AER generation", IEEE Trans. Neural Netw., vol.17, no. 3, pp. 771-788, May 2006
6. F. Gomez-Rodriguez and R. Paz-Vicente et al., "AER tools for communications and debugging", in Proc. IEEE Int. Symp. Circuits Syst., (ISCAS'06), May 2006, pp. 3253-3256