FPGA technology mapping with encoded libraries and staged priority cuts

Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09

Volumn , Issue , 2009, Pages 143-150

  Kennings, Andrew ^a   Vorwerk, Kristofer ^a   Kundu, Arun ^a   Pevzner, Val ^a   Fox, Andy ^a  

^a Actel Corp   (United States)

Author keywords

FPGA; Priority cuts; Synthesis; Technology mapping

Indexed keywords

CAD FLOW; FPGA; FPGA ARCHITECTURES; FPGA TECHNOLOGY; LOGIC BLOCKS; MAPPING ALGORITHMS; NUMERICAL RESULTS; PRIORITY CUTS; REAL CIRCUITS; SYNTHESIS; TECHNOLOGY MAPPING;

CONFORMAL MAPPING; LOGIC GATES; TECHNOLOGY;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 67650677773     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508128.1508151     Document Type: Conference Paper

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