Heuristics for area minimization in LUT-based FPGA technology mapping

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 11, 2006, Pages 2331-2340

  Manohararajah, Valavan ^b,c   Brown, Stephen D ^a,b,c   Vranesic, Zvonko G ^a,b,c  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c Altera Toronto Technology Center   (Canada)

Author keywords

Circuit optimization; Circuit synthesis; Design automation; Field programmable gate arrays; Logic design

Indexed keywords

CIRCUIT OPTIMIZATION; CIRCUIT SYNTHESIS; DESIGN AUTOMATION;

ALGORITHMS; HEURISTIC METHODS; LOGIC DESIGN; MAPPING; MATHEMATICAL MODELS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33750599310     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.882119     Document Type: Article

References (29)

1. J. Cong and Y. Ding, "Combinational logic synthesis for LUT based field programmable gate arrays," ACM Trans. Des. Autom. Electron. Syst., vol. 1, no. 2, pp. 145-204, Apr. 1996.
2. _, "An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 1, pp. 1-13, Jan. 1994.
3. _, "On area/depth tradeoff in LUT-based FPGA technology mapping," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no. 2, pp. 137-148, Jun. 1994.
4. Y. Kukimoto, R. K. Brayton, and P. Sawkar, "Delay-optimal technology mapping by DAG covering," in Proc. Des. Autom. Conf., San Francisco, CA, Jun. 1998, pp. 348-351.
5. I. Levin and R. Y. Pinter, "Realizing expression graphs using table-lookup FPGAs," in Proc. Eur. Des. Autom. Conf., Hamburg, Germany, Sep. 1993, pp. 306-311.
6. A. Farrahi and M. Sarrafzadeh, "Complexity of the lookup-table minimization problem for FPGA technology mapping," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 11, pp. 1319-1332, Nov. 1994.
7. S. Zhang, D. M. Miller, and J. M. Muzio, "Notes on the complexity of the lookup-table minimization problem for FPGA technology mapping," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 12, pp. 1588-1590, Dec. 1996.
8. K. Keutzer, "DAGON: Technology binding and local optimization by DAG matching," in Proc. Des. Autom. Conf., Miami Beach, FL, 1987, pp. 341-347.
9. R. J. Francis, J. Rose, and Z. G. Vranesic, "Technology mapping of lookup table-based FPGAs for performance," in Proc. IEEE Int. Conf. Comput.-Aided Des., Santa Clara, CA, Nov. 1991, pp. 568-571.
10. _, "Chortle-crf: Fast technology mapping for lookup table-based FPGAs," in Proc. ACM/IEEE Des. Autom. Conf., San Francisco, CA, Jun. 1991, pp. 227-233.
11. J. Cong and Y.-Y. Hwang, "Simultaneous depth and area minimization in LUT-based FGPA mapping," in Proc. ACM Int. Symp. FPGAs, Monterey, CA, Feb. 1995, pp. 68-74.
12. H. Li, S. Katkoori, and W. K. Mak, "Power minimization algorithms for LUT based FPGA technology mapping," ACM Trans. Des. Autom. Electron. Syst., vol. 9, no. 1, pp. 33-51, Jan. 2004.
13. J. Cong, C. Wu, and Y. Ding, "Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution," in Proc. ACM Int. Symp. FPGAs, Monterey, CA, Feb. 1999, pp. 29-35.
14. D. Chen and J. Cong, "DAOMap: A depth-optimal area optimization mapping algorithm for FPGA designs," in Proc. IEEE Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 2004, pp. 752-759.
15. H. Yang and D. F. Wong, "Edge-Map: Optimal performance driven technology mapping for iterative LUT based FPGA designs," in Proc. IEEE Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 1994, pp. 150-155.
16. J. Y. Lin, A. Jagannathan, and J. Cong, "Placement-driven technology mapping for LUT-based FPGAs," in Proc. ACM Int. Symp. FPGAs, Monterey, CA, Feb. 2003, pp. 121-126.
17. M. Schlag, J. Kong, and P. K. Chan, "Routability-driven technology mapping for lookup table-based FPGAs," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 1, pp. 13-26, Jan. 1994.
18. J. Rose, R. Francis, D. Lewis, and P. Chow, "Architecture of field-programmable gate arrays: The effect of logic block functionality on area efficiency," IEEE J. Solid-State Circuits, vol. 25, no. 5, pp. 1217-1225, Oct. 1990.
19. Virtex II Platform FPGA Data Sheet, 2002, San Jose, CA: Xilinx Inc. [Online]. Available: http://www.xilinx.com/apps/virtexapp.htm
20. Collaborative Benchmarking Laboratory, LGSynth93 Benchmark Suite. [Online]. Available: http://www.cbl.ncsu.edu/www/
21. E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. L. Sangiovanni- Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Univ. California at Berkeley, Berkeley. Tech. Report, Memo. No. UCB/ERL M92/41, 1992.
22. Altera Inc., Stratix II Device Handbook (Complete Two-Volume Set). Version 2.0, Jan. 2005.
23. J. Cong, J. Peck, and Y. Ding, "RASP: A general logic synthesis system for SRAM-based FPGAs," in Proc. ACM Int. Symp. FPGAs, Monterey, CA, Feb. 1996, pp. 137-143.
24. K. C. Chen, J. Cong, Y. Ding, A. Kahng, and P. Trajmar, "DAG-Map: Graph-based FPGA technology mapping for delay optimization," IEEE Des. Test Comput., vol. 9, no. 3, pp. 7-20, Sep. 1992.
25. A. Lu, G. Stenz, and F. M. Johannes, "Technology mapping for minimizing gate and routing area," in Proc. Conf. Des., Autom. Test Eur.. Paris, France: Le Palais des Congres de Paris, 1998, pp. 664-669.
26. V. Manohararajah, S. D. Brown, and Z. G. Vranesic, "Heuristics for area minimization in LUT-based FPGA technology mapping," in Proc. Int. Workshop Logic and Synthesis, Temecula Creek, CA, 2004, pp. 14-21.
27. MVSIS Group, MVSIS: Multi-Valued Logic Synthesis System, Berkeley: Univ. California Berkeley. [Online]. Available: http://www-cad.eecs. berkeley.edu/mvsis/
28. A. Mishchenko, S. Chatterjee, and R. Brayton, "An integrated technology mapping environment," in Proc. Int. Workshop Logic and Synthesis, Lake Arrowhead, CA, 2005, pp. 383-390.
29. S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, "Reducing structural bias in technology mapping," in Proc. Int. Workshop Logic and Synthesis, Lake Arrowhead, CA, 2005, pp. 375-382.