Factor cuts

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 143-150

  Chatterjee, Satrajit ^a   Mishchenko, Alan ^a   Brayton, Robert ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDED SIZE; COMPUTER-AIDED DESIGN; EXHAUSTIVE ENUMERATION; INTERNATIONAL CONFERENCES; LOGIC SYNTHESIS; MACRO CELLS; OPTIMALITY; RUN TIME; STRUCTURAL BIAS; TECHNOLOGY-MAPPING;

DESIGN; FACTORIZATION; HEURISTIC METHODS; HEURISTIC PROGRAMMING; STANDARDS;

CONFORMAL MAPPING;

EID: 39749174191     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320078     Document Type: Conference Paper

References (11)

1. Actel Corporation, "ProASIC3 Flash Family FPGAs Datasheet," Available from Actel website.
2. Berkeley Logic Synthesis Group, The ABC Logic Synthesis System, UC Berkeley. http://www.eecs.berkeley.edu/∼alanmi/abc/
3. D. Chai and A. Kuehlmann, "Building a Better Boolean Matcher and Symmetry Detector," In DATE '06, pp. 1079-1084.
4. S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, "Reducing Structural Bias in Technology Mapping," In ICCAD '05, pp. 519-526.
5. J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs," IEEE Trans. CAD, Vol. 13, No. 1 (January 1994), pp. 1-12.
6. J. Cong, C. Wu and Y. Ding, "Cut Ranking and Pruning: Enabling a general and efficient FPGA mapping solution," In FPGA '99, pp. 29-35.
7. M. Hutton et al., "Improving FPGA Performance and Area using an Adaptive Logic Module," In Field Programming Logic and Application 2004, pp. 135-144.
8. A. Ling, D. Singh and S. Brown, "FPGA Logic Synthesis using Quantified Boolean Satisfiability," In SAT '05, Springer LNCS Vol. 3569, pp. 444-450.
9. A. Mishchenko, S. Chatterjee and R. Brayton, "Improvements to Technology Mapping for LUT-based FPGAs," Proc. FPGA '06, pp. 41-49.
10. A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG Re-writing: A fresh look at combinational logic synthesis," In DAC '06, pp. 532-536.
11. P. Pan and Liu, "A New Retiming-based Technology Mapping Algorithm for LUT-based FPGAs," In ACM Int'l Symp. on FPGAs, pp. 35-42, 1998.