-
1
-
-
0028259317
-
Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs
-
J. Cong and Y. Ding, "Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs," in TCAD, 1994.
-
(1994)
TCAD
-
-
Cong, J.1
Ding, Y.2
-
3
-
-
0032681920
-
Cut ranking and pruning: Enabling a general and efficient fpga mapping solution
-
J. Cong, C. Wu, and Y. Ding, "Cut ranking and pruning: Enabling a general and efficient fpga mapping solution," in FPGA, 1999.
-
(1999)
FPGA
-
-
Cong, J.1
Wu, C.2
Ding, Y.3
-
5
-
-
84871375280
-
The stratix ii routing and logic architecture
-
Feb
-
D. Lewis and et al, "The stratix ii routing and logic architecture," in FPGA, Feb 2005.
-
(2005)
FPGA
-
-
Lewis, D.1
and et, al.2
-
7
-
-
0001277124
-
A survey of Boolean matching techniques for library binding
-
L. Benini and G. D. Micheli, "A survey of Boolean matching techniques for library binding," TODAES, vol. 2, no. 3, pp. 193-226, 1997.
-
(1997)
TODAES
, vol.2
, Issue.3
, pp. 193-226
-
-
Benini, L.1
Micheli, G.D.2
-
8
-
-
27944492443
-
-
A. Ling, D. Singh, and S. Brown, FPGA technology mapping: a study of optimality, in DAC, 2005.
-
A. Ling, D. Singh, and S. Brown, "FPGA technology mapping: a study of optimality," in DAC, 2005.
-
-
-
-
9
-
-
85165859540
-
-
S. Safarpour, A. Veneris, G. Baeckler, and R. Yuan, Efficient sat based boolean matching for fpga technology mapping, in DAC, 2006.
-
S. Safarpour, A. Veneris, G. Baeckler, and R. Yuan, "Efficient sat based boolean matching for fpga technology mapping," in DAC, 2006.
-
-
-
-
10
-
-
34748910665
-
Improved sat-based boolean matching using implicants for lut-based fpgas
-
J. Cong and K. Minkovich, "Improved sat-based boolean matching using implicants for lut-based fpgas," in FPGA, 2007.
-
(2007)
FPGA
-
-
Cong, J.1
Minkovich, K.2
-
11
-
-
50249101213
-
Fast boolean matching with dont cares
-
Z. Wei, D. Chai, A. Kuehlmann, and A. R. Newton, "Fast boolean matching with dont cares," in ISQED, 2006.
-
(2006)
ISQED
-
-
Wei, Z.1
Chai, D.2
Kuehlmann, A.3
Newton, A.R.4
-
12
-
-
0141740757
-
Solving difficult instances of boolean satisfiability in the presence of symmetry
-
F. Aloul, A. Ramani, I. Markov, and K. Sakallah, "Solving difficult instances of boolean satisfiability in the presence of symmetry," in TCAD, 2003.
-
(2003)
TCAD
-
-
Aloul, F.1
Ramani, A.2
Markov, I.3
Sakallah, K.4
-
13
-
-
41549121932
-
Generalized symmetries in boolean functions: Fast computation and application to boolean matching
-
J. S. Zhang, M. Chrzanowska-Jeske, A. Mishchenko, and J. R. Burch, "Generalized symmetries in boolean functions: Fast computation and application to boolean matching," in IWLS, 2004.
-
(2004)
IWLS
-
-
Zhang, J.S.1
Chrzanowska-Jeske, M.2
Mishchenko, A.3
Burch, J.R.4
-
14
-
-
85165862103
-
-
J. S. Zhang, A. Mishchenko, R. Brayton, and M. Chrzanowska-Jeske, Symmetry detection for large boolean functions using circuit representation, simulation and satisfiability, in DAC, 2006.
-
J. S. Zhang, A. Mishchenko, R. Brayton, and M. Chrzanowska-Jeske, "Symmetry detection for large boolean functions using circuit representation, simulation and satisfiability," in DAC, 2006.
-
-
-
-
15
-
-
50249102280
-
Exploiting Symmetry in SATBased Boolean Matching for Heterogeneous FPGA Technology Mapping,
-
07-265
-
Y. Hu, V. Shih, R. Majumdar, and L. He, "Exploiting Symmetry in SATBased Boolean Matching for Heterogeneous FPGA Technology Mapping," in Technical Report UCLA Engr 07-265, 2007
-
(2007)
Technical Report UCLA Engr
-
-
Hu, Y.1
Shih, V.2
Majumdar, R.3
He, L.4
-
16
-
-
50249150401
-
-
N. Een and N. Sorensso, http://www.cs.chalmers.se/Cs/Research/ FormalMethods/MiniSat/MiniSat.html.
-
-
-
Een, N.1
Sorensso, N.2
|