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Volumn , Issue , 2007, Pages 350-353

Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping

Author keywords

[No Author keywords available]

Indexed keywords

BM ALGORITHM; BOOLEAN MATCHING; BOOLEAN MATCHING PROBLEM; COMPUTER-AIDED DESIGN; FIELD-PROGRAMMABLE GATE ARRAYS; FPGA ARCHITECTURES; FPGA TECHNOLOGY MAPPING; INTERNATIONAL CONFERENCES; TECHNOLOGY-MAPPING;

EID: 50249102280     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397289     Document Type: Conference Paper
Times cited : (24)

References (17)
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  • 5
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    • D. Lewis and et al, "The stratix ii routing and logic architecture," in FPGA, Feb 2005.
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    • Benini, L.1    Micheli, G.D.2
  • 8
    • 27944492443 scopus 로고    scopus 로고
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  • 9
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  • 10
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    • (2007) FPGA
    • Cong, J.1    Minkovich, K.2
  • 12
    • 0141740757 scopus 로고    scopus 로고
    • Solving difficult instances of boolean satisfiability in the presence of symmetry
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    • (2003) TCAD
    • Aloul, F.1    Ramani, A.2    Markov, I.3    Sakallah, K.4
  • 13
    • 41549121932 scopus 로고    scopus 로고
    • Generalized symmetries in boolean functions: Fast computation and application to boolean matching
    • J. S. Zhang, M. Chrzanowska-Jeske, A. Mishchenko, and J. R. Burch, "Generalized symmetries in boolean functions: Fast computation and application to boolean matching," in IWLS, 2004.
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  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.