Efficient SAT-based Boolean matching for FPGA technology mapping

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 466-471

  Safarpour, Sean ^a   Veneris, Andreas ^a   Baeckler, Gregg ^b   Yuan, Richard ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b ALTERA CORPORATION   (United States)

Author keywords

Boolean matching; Boolean satisfiability; FPGA technology mapping

Indexed keywords

CONFORMAL MAPPING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); OPTIMIZATION; PROBLEM SOLVING; PROGRAMMABLE LOGIC CONTROLLERS; SPACE TIME ADAPTIVE PROCESSING;

BOOLEAN MATCHING; BOOLEAN MATCHING PROBLEM; BOOLEAN SATISFIABILITY; FPGA TECHNOLOGY MAPPING;

BOOLEAN ALGEBRA;

EID: 34547183601     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147034     Document Type: Conference Paper

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