Logic synthesis and technology mapping of MUX-based FPGAs for high performance and low power

IEEE Region 10 Annual International Conference, Proceedings/TENCON

Volumn D, Issue , 2004, Pages

  Marik, Maitrali ^a   Pal, Ajit ^b  

^a IBM INDIA RESEARCH LAB   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; BOOLEAN FUNCTIONS; OPTIMIZATION; PROBLEM SOLVING;

BENCHMARK CIRCUITS; LOGIC SYNTHESIS; TECHNOLOGY MAPPING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 27944492798     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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4. E. Sentovich, et al. SIS: A system for sequential circuit synthesis, Technical report, University of Berkley, 1992.
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7. P. Buch, A. Narayana, A. R. Newton, and A. S. Vincentelli, Logic Synthesis for Large Pass Transistor Circuits, IEEE/ACM Proc. ICCAD, pp 663-670, Nov. 1997.
8. Espejo, L.Entrena, E. San Millan, E. Olias, Logic restructuring for MUX-based FPGAs, In EUROMICRO, pages 161-168, 1999.
9. th International Conference on VLSI Design, pp. 209-212, Jan. 2003.