메뉴 건너뛰기




Volumn , Issue , 2008, Pages 47-55

WireMap: FPGA technology mapping for improved routability

Author keywords

Area flow; Cut enumeration; Edge flow; FPGA; Technology mapping

Indexed keywords

AREA FLOW; CUT ENUMERATION; EDGE FLOW; FPGA; TECHNOLOGY MAPPING;

EID: 70349332327     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1344671.1344680     Document Type: Conference Paper
Times cited : (14)

References (19)
  • 1
    • 62649093474 scopus 로고    scopus 로고
    • Altera. Stratix III Device Handbook, http://www.altera.com/literature/hb/ stx3/stratix3-handbook.pdf
    • Stratix III Device Handbook
  • 3
    • 84869607999 scopus 로고    scopus 로고
    • Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Release 61225
    • Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, Release 61225. http://www.eecs. berkeley.edu/̃alanmi/abc/
  • 6
    • 16244418071 scopus 로고    scopus 로고
    • DAOmap: A depth-optimal area optimization mapping algorithm for FPGA designs
    • D. Chen and J. Cong. "DAOmap: A depth-optimal area optimization mapping algorithm for FPGA designs," Proc. ICCAD'04, pp. 752-757.
    • Proc. ICCAD'04 , pp. 752-757
    • Chen, D.1    Cong, J.2
  • 7
    • 0028259317 scopus 로고
    • FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
    • Jan
    • J. Cong and Y. Ding, "FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs", IEEE TCAD, Vol. 13(1), Jan. 1994, pp. 1-12
    • (1994) IEEE TCAD , vol.13 , Issue.1 , pp. 1-12
    • Cong, J.1    Ding, Y.2
  • 8
    • 0032681920 scopus 로고    scopus 로고
    • Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution
    • J. Cong, C. Wu, and Y. Ding, "Cut ranking and pruning: Enabling a general and efficient FPGA mapping solution," Proc. FPGA'99, pp. 29-36.
    • (1999) Proc. FPGA , pp. 29-36
    • Cong, J.1    Wu, C.2    Ding, Y.3
  • 10
    • 0031200347 scopus 로고    scopus 로고
    • Logic decomposition during technology mapping
    • E. Lehman, Y. Watanabe, J. Grodstein, and H. Harkness, "Logic decomposition during technology mapping," IEEE Trans. CAD, vol. 16(8), 1997, pp. 813-833.
    • (1997) IEEE Trans. CAD , vol.16 , Issue.8 , pp. 813-833
    • Lehman, E.1    Watanabe, Y.2    Grodstein, J.3    Harkness, H.4
  • 11
    • 16244396261 scopus 로고    scopus 로고
    • Heuristics for area minimization in LUT-based FPGA technology mapping
    • V. Manohara-rajah, S. D. Brown, and Z. G. Vranesic, "Heuristics for area minimization in LUT-based FPGA technology mapping," Proc. IWLS '04, pp. 14-21.
    • Proc. IWLS '04 , pp. 14-21
    • Manohara-rajah, V.1    Brown, S.D.2    Vranesic, Z.G.3
  • 12
  • 13
    • 33846545005 scopus 로고    scopus 로고
    • DAG-aware AIG rewriting: A fresh look at combinational logic synthesis
    • A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-aware AIG rewriting: A fresh look at combinational logic synthesis", Proc. DAC'06, pp. 532-536.
    • Proc. DAC'06 , pp. 532-536
    • Mishchenko, A.1    Chatterjee, S.2    Brayton, R.3
  • 17
    • 0031624162 scopus 로고    scopus 로고
    • A new retiming-based technology mapping algorithm for LUT-based FPGAs
    • P. Pan and C.-C. Lin, "A new retiming-based technology mapping algorithm for LUT-based FPGAs," Proc. FPGA '98, pp. 35-42.
    • (1998) Proc. FPGA , pp. 35-42
    • Pan, P.1    Lin, C.-C.2
  • 19
    • 70349368614 scopus 로고    scopus 로고
    • Xilinx White Paper. Achieving higher system performance with the Virtex-5 family of FPGAs, http://direct.xilinx.com/bvdocs/whitepapers/ wp245.pdf
    • Xilinx White Paper. "Achieving higher system performance with the Virtex-5 family of FPGAs", http://direct.xilinx.com/bvdocs/whitepapers/ wp245.pdf


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.