A compiler-directed data prefetching scheme for chip multiprocessors

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP

Volumn , Issue , 2009, Pages 209-218

  Son, Seung Woo ^a   Kandemir, Mahmut ^a   Karakoy, Mustafa ^b   Chakrabarti, Dhruva ^c  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

^c HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Chip multiprocessors; Compiler; Helper thread; Prefetching

Indexed keywords

BENCHMARK SUITES; CHIP MULTIPROCESSOR; CHIP MULTIPROCESSORS; COMPILER; DATA-PREFETCHING; DEGRADED PERFORMANCE; EXPERIMENTAL DATA; HELPER THREAD; ITS DATA; MEMORY ACCESS LATENCY; MULTI-THREADED APPLICATION; NEGATIVE INTERACTION; ON-CHIP CACHE; ON-CHIP MULTIPROCESSOR; OPTIMAL SCHEME; PARALLEL EXECUTIONS; PERFORMANCE IMPROVEMENTS; PREFETCH; PREFETCHES; PREFETCHING; PROGRAM PHASIS; SHARED CACHE; SIMULATION PARAMETERS; STATIC COMPILER;

BENCHMARKING; MULTIPROCESSING SYSTEMS; PARALLEL PROGRAMMING; SYSTEMS ANALYSIS;

PROGRAM COMPILERS;

EID: 67650091160     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1504176.1504208     Document Type: Conference Paper

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