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Volumn 19, Issue 1, 2001, Pages 71-109

Architectural and compiler support for effective instruction prefetching: A cooperative approach

Author keywords

B.3.2 Memory Structures : Design Styles Cache memories; Compiler optimization; D.3.4 Programming Languages : Processors Compilers; Design; Experimentation; Instruction prefetching; Optimization; Performance

Indexed keywords


EID: 0042366306     PISSN: 07342071     EISSN: None     Source Type: Journal    
DOI: 10.1145/367742.367786     Document Type: Article
Times cited : (26)

References (29)
  • 3
    • 0029192907 scopus 로고
    • Compiler techniques for data prefetching on the powerPC
    • (PACT '95, Limassol, Cyprus, June 27-29), L. Bic, P. Evripidou, W. Böhm, and J.-L. Gaudiot, Chairs. IFIP Working Group on Algol, Manchester, UK
    • BERNSTEIN, D., COHEN, D., AND FREUND, A. 1995. Compiler techniques for data prefetching on the PowerPC. In Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques (PACT '95, Limassol, Cyprus, June 27-29), L. Bic, P. Evripidou, W. Böhm, and J.-L. Gaudiot, Chairs. IFIP Working Group on Algol, Manchester, UK, 19-26.
    • (1995) Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques , pp. 19-26
    • Bernstein, D.1    Cohen, D.2    Freund, A.3
  • 4
    • 0030651783 scopus 로고    scopus 로고
    • Target prediction for indirect jumps
    • (ISCA '97, Denver, CO, June 2-4), A. R. Pleszkun and T. Mudge, Chairs. ACM Press, New York, NY
    • CHANG, P.-Y., HAO, E., AND PATT, Y. N. 1997. Target prediction for indirect jumps. In Proceedings of the 24th International Symposium on Computer Architecture (ISCA '97, Denver, CO, June 2-4), A. R. Pleszkun and T. Mudge, Chairs. ACM Press, New York, NY, 274-283.
    • (1997) Proceedings of the 24th International Symposium on Computer Architecture , pp. 274-283
    • Chang, P.-Y.1    Hao, E.2    Patt, Y.N.3
  • 5
    • 0031594010 scopus 로고    scopus 로고
    • Accurate indirect branch prediction
    • (ISCA '98, Barcelona, Spain, June 27-July 1), D. DeGroot, Ed. IEEE Press, Piscataway, NJ
    • DRIESEN, K. AND HOLZLE, U. 1998a. Accurate indirect branch prediction. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA '98, Barcelona, Spain, June 27-July 1), D. DeGroot, Ed. IEEE Press, Piscataway, NJ, 167-178.
    • (1998) Proceedings of the 25th Annual International Symposium on Computer Architecture , pp. 167-178
    • Driesen, K.1    Holzle, U.2
  • 6
    • 0032312775 scopus 로고    scopus 로고
    • The cascaded predictor: Economical and adaptive branch target prediction
    • (MICRO-31, Dallas, TX, Nov. 30-Dec. 2), J. Bondi and J. Smith, Chairs. IEEE Computer Society Press, Los Alamitos, CA
    • DRIESEN, K. AND HÖLZLE, U. 1998b. The cascaded predictor: Economical and adaptive branch target prediction. In Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-31, Dallas, TX, Nov. 30-Dec. 2), J. Bondi and J. Smith, Chairs. IEEE Computer Society Press, Los Alamitos, CA, 249-258.
    • (1998) Proceedings of the 31st Annual ACM/IEEE International Symposium on Microarchitecture , pp. 249-258
    • Driesen, K.1    Hölzle, U.2
  • 7
    • 0031334454 scopus 로고    scopus 로고
    • Procedure placement using temporal ordering information
    • (MICRO 30, Research Triangle Park, NC, Dec. 1-3), M. Smotherman and T. Conte, Chairs. IEEE Computer Society Press, Los Alamitos, CA
    • GLOY, N., BLACKWELL, T., SMITH, M. D., AND CALDER, B. 1997. Procedure placement using temporal ordering information. In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 30, Research Triangle Park, NC, Dec. 1-3), M. Smotherman and T. Conte, Chairs. IEEE Computer Society Press, Los Alamitos, CA, 303-313.
    • (1997) Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture , pp. 303-313
    • Gloy, N.1    Blackwell, T.2    Smith, M.D.3    Calder, B.4
  • 10
    • 0024668117 scopus 로고
    • Achieving high instruction cache performance with an optimizing compiler
    • (ISCA '89, Jerusalem, Israel, May 28-June 1), J.-C. Syre, Chair. ACM Press, New York, NY
    • HWU, W. AND CHANG, P. 1989. Achieving high instruction cache performance with an optimizing compiler. In Proceedings of the 16th Annual International Symposium on Computer Architecture (ISCA '89, Jerusalem, Israel, May 28-June 1), J.-C. Syre, Chair. ACM Press, New York, NY, 242-251.
    • (1989) Proceedings of the 16th Annual International Symposium on Computer Architecture , pp. 242-251
    • Hwu, W.1    Chang, P.2
  • 11
    • 0030677583 scopus 로고    scopus 로고
    • Prefetching using Markov predictors
    • (ISCA '97, Denver, CO, June 2-4), A. R. Pleszkun and T. Mudge, Chairs. ACM Press, New York, NY
    • JOSEPH, D. AND GRUNWALD, D. 1997. Prefetching using Markov predictors. In Proceedings of the 24th International Symposium on Computer Architecture (ISCA '97, Denver, CO, June 2-4), A. R. Pleszkun and T. Mudge, Chairs. ACM Press, New York, NY, 252-263.
    • (1997) Proceedings of the 24th International Symposium on Computer Architecture , pp. 252-263
    • Joseph, D.1    Grunwald, D.2
  • 12
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • (ISCA '90, Seattle, WA, May). IEEE Press, Piscataway, NJ
    • JOUPPI, N. 1990. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th International Symposium on Computer Architecture (ISCA '90, Seattle, WA, May). IEEE Press, Piscataway, NJ, 364-373.
    • (1990) Proceedings of the 17th International Symposium on Computer Architecture , pp. 364-373
    • Jouppi, N.1
  • 17
    • 84963593269 scopus 로고
    • Profile guided code positioning
    • (SIGPLAN '90, White Plains, NY, June 20-22), B. N. Fischer, Chair. ACM Press, New York, NY
    • PETTIS, K. AND HANSEN, R. 1990. Profile guided code positioning. In Proceedings of the Conference on Programming Language Design and Implementation (SIGPLAN '90, White Plains, NY, June 20-22), B. N. Fischer, Chair. ACM Press, New York, NY, 16-27.
    • (1990) Proceedings of the Conference on Programming Language Design and Implementation , pp. 16-27
    • Pettis, K.1    Hansen, R.2
  • 18
    • 0030381715 scopus 로고    scopus 로고
    • Wrong-path instruction prefetching
    • (MICRO 29, Paris, France, Dec. 2-4), S. Melvin and S. Beaty, Chairs. IEEE Computer Society Press, Los Alamitos, CA
    • PIERCE, J. AND MUDGE, T. 1996. Wrong-path instruction prefetching. In Proceedings of the 29th annual IEEE/ACM international symposium on Microarchitecture (MICRO 29, Paris, France, Dec. 2-4), S. Melvin and S. Beaty, Chairs. IEEE Computer Society Press, Los Alamitos, CA, 165-175.
    • (1996) Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture , pp. 165-175
    • Pierce, J.1    Mudge, T.2
  • 21
  • 22
    • 0018106484 scopus 로고
    • Sequential program prefetching in memory hierarchies
    • SMITH, A. 1978. Sequential program prefetching in memory hierarchies. IEEE Computer 11, 2, 7-21.
    • (1978) IEEE Computer , vol.11 , Issue.2 , pp. 7-21
    • Smith, A.1
  • 23
    • 0020177251 scopus 로고
    • Cache memories
    • Sept.
    • SMITH, A. J. 1982. Cache memories. ACM Comput. Surv. 14, 3 (Sept.), 473-530.
    • (1982) ACM Comput. Surv. , vol.14 , Issue.3 , pp. 473-530
    • Smith, A.J.1
  • 24
    • 0041358632 scopus 로고
    • Prefetching in supercomputer instruction caches
    • (Supercomputing '92, Minneapolis, MN, Nov. 16-20), R. Werner, Ed. IEEE Computer Society Press, Los Alamitos, CA
    • SMITH, J. E. AND HSU, W.-C. 1992. Prefetching in supercomputer instruction caches. In Proceedings of the 1992 Conference on Supercomputing (Supercomputing '92, Minneapolis, MN, Nov. 16-20), R. Werner, Ed. IEEE Computer Society Press, Los Alamitos, CA, 588-597.
    • (1992) Proceedings of the 1992 Conference on Supercomputing , pp. 588-597
    • Smith, J.E.1    Hsu, W.-C.2
  • 25
    • 0031333687 scopus 로고    scopus 로고
    • Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order
    • (MICRO 30, Research Triangle Park, NC, Dec. 1-3), M. Smotherman and T. Conte, Chairs. IEEE Computer Society Press, Los Alamitos, CA
    • STARK, J., RACUNAS, P., AND PATT, Y. N. 1997. Reducing the performance impact of instruction cache misses by writing instructions into the reservation stations out-of-order. In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 30, Research Triangle Park, NC, Dec. 1-3), M. Smotherman and T. Conte, Chairs. IEEE Computer Society Press, Los Alamitos, CA, 34-43.
    • (1997) Proceedings of the 30th Annual Ieee/acm International Symposium on Microarchitecture , pp. 34-43
    • Stark, J.1    Racunas, P.2    Patt, Y.N.3
  • 26
    • 0009571347 scopus 로고
    • Subroutine call/return stack
    • Apr.
    • WEBB, C. F. 1988. Subroutine call/Return stack. IBM Tech. Discl. Bull. 30, 11 (Apr.).
    • (1988) IBM Tech. Discl. Bull. , vol.30 , Issue.11
    • Webb, C.F.1
  • 27
    • 0029666632 scopus 로고    scopus 로고
    • Instruction prefetching of system codes with layout optimized for reduced cache misses
    • (Philadelphia, PA, May). ACM Press, New York, NY
    • XIA, C. AND TORRELLAS, J. 1996. Instruction prefetching of system codes with layout optimized for reduced cache misses. In Proceedings of the 23rd International Symposium on Computer Architecture (Philadelphia, PA, May). ACM Press, New York, NY, 271-282.
    • (1996) Proceedings of the 23rd International Symposium on Computer Architecture , pp. 271-282
    • Xia, C.1    Torrellas, J.2
  • 28
    • 0030129806 scopus 로고    scopus 로고
    • The MIPS R10000 superscalar microprocessor
    • Apr.
    • YEAGER, K. C. 1996. The MIPS R10000 superscalar microprocessor. IEEE Micro 16, 2 (Apr.), 28-40.
    • (1996) IEEE Micro , vol.16 , Issue.2 , pp. 28-40
    • Yeager, K.C.1
  • 29


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.