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Volumn 2006, Issue , 2006, Pages 144-153

Efficient emulation of hardware prefetchers via event-driven helper threading

Author keywords

Helper threading; Multi core architectures; Prefetching

Indexed keywords

HELPER THREADING; MULTI CORE ARCHITECTURES; PREFETCHING; THROUGHPUT ORIENTED COMPUTING;

EID: 34247120722     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1152154.1152178     Document Type: Conference Paper
Times cited : (25)

References (26)
  • 6
    • 34247116403 scopus 로고    scopus 로고
    • http://www.spec.org/osg/cpu2000/.
  • 8
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proc. 17th Intl. Symp. on Computer Architecture, 1990.
    • (1990) Proc. 17th Intl. Symp. on Computer Architecture
    • Jouppi, N.P.1
  • 12
    • 0034839064 scopus 로고    scopus 로고
    • Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
    • C.-K. Luk. Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors. In Proc. 28th Intl. Symp. on Computer architecture, 2001.
    • (2001) Proc. 28th Intl. Symp. on Computer architecture
    • Luk, C.-K.1
  • 21
    • 0003450887 scopus 로고    scopus 로고
    • Cacti 3.0: An integrated cache timing, power, and area model
    • Tech. report WRL-2001-2, Compaq Western Research Laboratory, December
    • P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model. Tech. report WRL-2001-2, Compaq Western Research Laboratory, December 2001.
    • (2001)
    • Shivakumar, P.1    Jouppi, N.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.