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Volumn , Issue , 2009, Pages 13-18

NBTI-Aware statistical circuit delay assessment

Author keywords

[No Author keywords available]

Indexed keywords

AGING EFFECTS; ANALYTICAL MODEL; CIRCUIT DELAY DISTRIBUTIONS; CIRCUIT DELAYS; DELAY SPREAD; MITIGATION TECHNIQUES; PMOS NBTI;

EID: 67649671613     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810263     Document Type: Conference Paper
Times cited : (12)

References (14)
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  • 2
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  • 3
    • 34347269880 scopus 로고    scopus 로고
    • Modeling and minimization of PMOS NBTI effect for robust nanometer design
    • July, Pages
    • R. Vattikonda, W. Wang, Y. Cao, "Modeling and minimization of PMOS NBTI effect for robust nanometer design", ACM/IEEE Design Automation Conference, July 2006, Page(s): 1047-1052
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    • Vattikonda, R.1    Wang, W.2    Cao, Y.3
  • 4
    • 51549119555 scopus 로고    scopus 로고
    • Seperation Method of Hole Trapping and Interface Trap Generation and Their Roles in NBTI Reaction-Diffusion Model
    • Pages
    • J. H. Lee, W. H. Wu, A. E. Islam, M. A. Alam, A. S. Oates, "Seperation Method of Hole Trapping and Interface Trap Generation and Their Roles in NBTI Reaction-Diffusion Model", IEEE IRPS 2008, Page(s): 745 -746
    • (2008) IEEE IRPS , pp. 745-746
    • Lee, J.H.1    Wu, W.H.2    Islam, A.E.3    Alam, M.A.4    Oates, A.S.5
  • 5
    • 40549122135 scopus 로고    scopus 로고
    • Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation
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    • A. E. Islam, H. Kufluoglu, D. Varghese, S. Mahapatra, M. A. Alam, "Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation", IEEE Tran. On Electron Devices, Volume 54, Issue 9, Sept 2007, Page(s): 2143-154
    • (2007) IEEE Tran. On Electron Devices , vol.54 , Issue.9 , pp. 2143-2154
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  • 6
    • 49549122051 scopus 로고    scopus 로고
    • An efficient method to identify critical gates under circuit aging
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    • W. Wang, Z. Wei, S. Yang, Y. Cao, "An efficient method to identify critical gates under circuit aging", IEEE/ACM Intl. Conf. On Comp. Aided Design, Nov. 2007, Page(s): 735-740
    • (2007) IEEE/ACM Intl. Conf. On Comp. Aided Design , pp. 735-740
    • Wang, W.1    Wei, Z.2    Yang, S.3    Cao, Y.4
  • 7
    • 37549010759 scopus 로고    scopus 로고
    • Circuit Failure Prediction and Its Application to Transistor Aging
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    • M. Agarwal, B. C. Paul, M. Zhang, S. Mitra, "Circuit Failure Prediction and Its Application to Transistor Aging", IEEE VLSI Test Symposium, 2007, Page(s): 277-286
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    • Agarwal, M.1    Paul, B.C.2    Zhang, M.3    Mitra, S.4
  • 8
    • 41549122836 scopus 로고    scopus 로고
    • Silicon Odometer: An On-chip Reliability Monitor for Frequency Degradation of Digital Circuits
    • April, Pages
    • T. -H. Kim, R. Persaud, C. H. Kim, "Silicon Odometer: An On-chip Reliability Monitor for Frequency Degradation of Digital Circuits", IEEE Journal of Solid-State Circuits, Volume 43, No. 4, April 2008, Page(s): 874-880
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  • 9
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  • 11
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  • 12
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.