Statistical timing for parametric yield prediction of digital integrated circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 11, 2006, Pages 2376-2391

  Jess, Jochen A G ^a,b   Kalafala, Kerim ^c   Naidu, Srinath R ^b,d   Otten, Ralph H J M ^a,b   Visweswariah, Chandu ^a,e  

^a IEEE   (Netherlands)

^b EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c IBM MICROELECTRONICS   (United States)

^d Magma Design Automation Pvt Ltd   (India)

^e IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Digital integrated circuits; Timing

Indexed keywords

EINSTIMER STATIC TIMING ANALYZER; PATH-BASED ALGORITHMS; PROBABILISTIC QUANTITY; STATISTICAL TIMING ANALYSIS;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; NUMERICAL ANALYSIS; STATISTICAL METHODS; TIMING CIRCUITS;

DIGITAL INTEGRATED CIRCUITS;

EID: 33750603321     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.881332     Document Type: Article

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