Assessment of a 90nm PMOS NBTI in the form of products failure rate

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2005, Pages 89-94

  Masuda, Hiroo ^a   Pierce, Donald G ^b   Nishitsuru, Kazunori ^c   Machida, Ken ^d  

^a SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

^b Sandia Technologies Inc   (United States)

^c YOKOGAWA ANALYTICAL SYSTEMS INC   (Japan)

^d Mathematical Systems Inc   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DEGRADATION; MICROELECTRONICS; PRODUCT DEVELOPMENT; TRANSISTORS;

BUM-IN TESTS; GIGA-TRANSISTOR; PMOS NBTI;

MOS DEVICES;

EID: 27644490539     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. D. J. Klinger et al.,; AT&T Reliability Manual; 1990.
2. A. G. Sabnis et al.;VLSI Electronic microstructure Science; 1990.
3. D.L. Grosh; A Primer of Reliability Theory, 1989.
4. E. S. Snyder et al.; SPI Vol.1802 Microelectronics Manufacturing and Reliability, 1992.
5. V. Rana, J. Educato, S. Parikh, M. Naik, T. Pan, P. Hey, D. Yost, D. Pierce: Proc. of Advanced Metallization Conference, Sept. 1999.
6. V. Huard, et al.; Proc. IEEE 2003IRPS, pp 178-182