Time Management for Low-Power Design of Digital Systems

Journal of Low Power Electronics

Volumn 4, Issue 3, 2008, Pages 410-419

  Semião, Jorge ^a,e   Freijedo, Judit F ^b   Rodriguez Andina, Juan J ^b   Vargas, Fabian ^c   Santos, Marcelino B ^d,e   Teixeira, Isabel C ^d,e   Teixeira, J Paulo ^d,e  

^a UNIVERSITY OF ALGARVE   (Portugal)

^b UNIVERSITY OF VIGO   (Spain)

^c PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^d INSTITUTO SUPERIOR TÉCNICO   (Portugal)

^e INESC ID   (Portugal)

Author keywords

Delay Fault; Power Supply Voltage and Temperature Variations; Process; Time Borrowing; Time Management

Indexed keywords

CLOCKS; FAULT DETECTION; PROCESSING; SEMICONDUCTOR STORAGE;

DELAY FAULTS; DETECTION CAPABILITY; NANO-CMOS TECHNOLOGIES; POWER SUPPLY VOLTAGE; POWER SUPPLY VOLTAGE AND TEMPERATURE VARIATIONS; TIME BORROWING; TIME MANAGEMENT; UNDERLYING PRINCIPLES;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 67649562607     PISSN: 15461998     EISSN: 15462005     Source Type: Journal    
DOI: 10.1166/jolpe.2008.194     Document Type: Article

References (26)

1. J. Jaffari and M. Anis, Statistical thermal profile considering process variations: Analysis and applications. IEEE Transactions on CAD of Integrated Circuits and Systems 27, 1027 (2008).
2. A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, and M. Poncino, Dynamic thermal clock skew compensation using tunable delay buffers. Proceedings of the International Symposium on Low Power Electronics and Design (2006), pp. 162-167.
3. A. H. Ajami, K. Banerjee, and M. Pedram, Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Transactions on Computer-Aided Design 24, 849 (2005).
4. M. Pedram and J. M. Rabaey, Power Aware Design Methodologies, Kluwer Academic Publishers, Norwell, MA, USA (2002).
5. S. Ravi, R. Parekhji, and J. Saxena, Low power test for nanometer system-on-chips (SoCs). Journal of Low Power Electronics 4, 81 (2008).
6. S. Bhunia and K. Roy, Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self repair solutions. Proceedings of the International Test Conference (2007), Lecture 2.1, pp. 1-10.
7. S. Ravi, Power-aware test: Challenges and solutions. Proceedings of the International Test Conference (2007), Lecture 2.2, pp. 1-10.
8. D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, N. S. Kim, and K. Flautner, Razor: Circuit-level correction of timing errors for low-power operation. IEEE Micro 24, 10 (2004).
9. B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, Theoretical and practical limits of dynamic voltage scaling. Proceedings of the ACM/IEEE Design Automation Conference (2004), pp. 868-873.
10. S. Khursheed, U. Ingelsson, P. Rosinger, B. M. Al-Hashimi, and P. Harrod, Bridging fault test method with adaptive power management awareness. IEEE Transactions on CAD of Integrated Circuits and Systems 27, 1117 (2008).
11. S. G. Narendra and A. Chandrakasan (eds.), Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems), Springer-Verlag, New York, Inc., Secaucus, NJ, USA (2005).
12. T. Steinecke, W. John, H. Koehne, and M. Schmidt, EMC modeling and simulation on chip level. IEEE International Symposium on Electromagnetic Compatibility (EMC), August, Montreal, Canada (2001), Vol. 2, pp. 1191-1196.
13. J. Semião, M. Rodriguez-Irago, L. Piccoli, F. Vargas, M. B. Santos, I. C. Teixeira, J. J. Rodriguez-Andina, and J. P. Teixeira, Signal integrity enhancement in digital circuits in the presence of power grid activity. IEEE Design & Test of Computers 25, 452 (2008).
14. V. G. Oklobdzija, Clocking and clocked storage elements in a multi-gigahertz environment. IBM Journal of Research and Development 47, 567 (2003).
15. K. Bowman, J. Tschanz, M. Khellah, M. Ghoneima, Y. Ismail, and V. De, Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. Proceedings of the International Symposium on Low Power Electronics and Design (2006), pp. 79-84.
16. J. Wang, D. M. H. Walker, A. Majhi, B. Kruseman, G. Gronthoud, L. E. Villagra, P. van de Wiel, and S. Eichenberger, Power supply noise in delay testing. Proceedings of the International Test Conference (2006), paper 17.3.
17. R. Saleh, D. Overhauser, and S. Taylor. Full-chip verification of UDSM designs. Proceedings of the International Conference on Computer Aided Design (1998), pp. 453-460.
18. A. Kahng, S. Muddu, and E. Sarto, Interconnect optimization strategies for high-performance VLSI designs. Proceedings of the International Conference on VLSI Design (1999), pp. 464-469.
19. G. Jung, V. Perepelitsa, and G. Sobelman, Time borrowing in highspeed functional units using skew-tolerant domino circuits. Proceedings of IEEE International Symposium on Circuits and Systems 5, 641 (2000).
20. N. Sirisantana and K. Roy, A time borrowing selectively clocked skew logic for high-performance circuits in scaled technologies. Proceedings of the 29th European Solid-State Circuits Conference (2003).
21. K. Chung and S. Gupta, Structural delay testing of latch-based highspeed pipelines with time borrowing. Proceedings of the International Test Conference (2003), pp. 1089-1097.
22. J. Semião, M. Rodriguez-Irago, L. Piccoli, F. Vargas, M. B. Santos, I. C. Teixeira, J. J. Rodríguez Andina, and J. P. Teixeira, Digital circuit signal integrity enhancement by monitoring power grid activity. Proc. IEEE Latin American Test Workshop (LATW'07), March (2007).
23. J. Semião, J. Freijedo, J. Rodríguez-Andina, F. Vargas, M. B. Santos, I. C. Teixeira, and J. P. Teixeira, Mixed-signal design of dynamic delay buffers to improve tolerance to power supply and temperature variations. Proceedings of the 13th International Mixed Signals Testing Workshop (IMSTW'07), June, Póvoa de Varzim, Portugal (2007), paper 2.2, pp. 130-135.
24. J. Semião, J. J. Rodriguez-Andina, F. Vargas, M. B. Santos, I. Teixeira, and J. P. Teixeira, Improving the tolerance of pipeline based circuits to power supply or temperature variations. Proc. of the 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07), September, Rome, Italy (2007), pp. 303-311.
25. F. Como, M. Sonza Reorda, and G. Squillero, RT-level ITC'99 benchmarks and first ATPG results. IEEE Design & Test of Computers 17, 44 (2000).
26. The Free Open Cores web page, http://www.opencores.org (2008).