Time borrowing in high-speed functional units using skew-tolerant domino circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2000, Pages V-641-V-644

  Jung, Gunok ^a   Perepelitsa, Victoria ^a   Sobelman, Gerald E ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0033716179     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2000.857542     Document Type: Article

References (9)

1. D. Harris M. A. Horowitz Skew-Tolerant Domino Circuits IEEE Journal of Solid-State Circuits 32 11 1702 1711 November 1997
2. D. Harris Skew-Tolerant Circuit Design November 1998 Stanford University
3. D. Harris Opportunistic Time-Borrowing Domino Logic 14 May 1996 U.S. 5,517,136
4. K. Bernstein High Speed CMOS Design Styles 1998 Kluwer Academic Publishers 8
5. J. Wang Area-Time Analysis of Carry Lookahead Adders Using Enhanced Multiple Output Domino Logic Proceedings, IEEE International Symposium on Circuits and Systems 4 59 62 Proceedings, IEEE International Symposium on Circuits and Systems 1994
6. Z. Wang Fast Adders using Enhanced Multiple-Output Domino Logic IEEE Journal of Solid-State Circuits 32 2 206 214 February 1997
7. S. Waser M. J. Flynn Introduction to Arithmetic for Digital System Design 1982 CBS Publishing 3
8. I. S. Hwang A. L. Fisher Ultra Fast Compact 32-bit CMOS Adder in Multiple-Output Domino Logic IEEE Journal of Solid-State Circuits 24 358 369 1989
9. O. J. Bedrij Carry-Select Adder IRE Trans. on Electronic Computers EC-11 340 346 1962