Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 79-84

  Bowman, Keith ^a   Tschanz, James ^a   Khellah, Muhammad ^a   Ghoneima, Maged ^b   Ismail, Yehea ^b   De, Vivek ^a  

^a INTEL RESEARCH   (United States)

^b Northwestern University   (United States)

Author keywords

Interconnect; Intra die variations; Multi cycle interconnect; Parameter fluctuations; Parameter variations; Time borrowing; Variation tolerant; Within die variations

Indexed keywords

MULTI-CYCLE INTERCONNECT; PARAMETER FLUCTUATIONS; PARAMETER VARIATIONS; VARIATION TOLERANT; WITHIN-DIE VARIATIONS;

COMPUTER SIMULATION; DELAY CONTROL SYSTEMS; FLIP FLOP CIRCUITS; RANDOM PROCESSES; STATISTICAL METHODS;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 34247189598     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165592     Document Type: Conference Paper

References (14)

1. K. A. Bowman, Steven G. Duvall, and J. D. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE JSSC, pp. 183-190, Feb. 2002.
2. th DAC Proc., June, 2003, pp. 338-342.
3. H. Masuda, S. Ohkawa, A. Kurokawa, and M. Aoki, "Challenge: Variability Characterization and Modeling for 65- to 90-nm Processes," in IEEE CICC, Sept. 2005, pp. 593-600.
4. st Century," Proc. IEEE, pp. 306-324, Mar. 2001.
5. M. T. Bohr, "Interconnect Scaling - The Real Limiter to High Performance ULSI," in IEEE IEDM, Dec. 1995, pp. 241-244.
6. V. De and S. Borkar, "Technology and Design Challenges for Low Power and High Performance," in Proc. ISLPED, Aug. 1999, pp. 163-168.
7. M. Khellah, et al., "A Skewed Repeater Interconnect Architecture for On-Chip Energy Reduction in Microprocessors," in IEEE Proc. 2005 ICCD, Oct. 2005, pp. 253-257.
8. V. G. Oklobdzija, The Computer Engineering Handbook, CRC Press, 2002.
9. D. Harris and M. A. Horowitz, "Skew-Tolerant Domino Circuits," IEEE JSSC, pp. 1702-1711, Nov. 1997.
10. H. Partovi, et al., "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements," in IEEE ISSCC, Feb. 1996, pp. 138-139.
11. V. G. Oklobdzija, "Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment," IBM J. Res. & Dev., pp. 567-583, Sept. 2003.
12. J. A. McNeill, "Jitter in Ring Oscillators," IEEE JSSC, pp. 870-879, June 1997.
13. M. Mansuri and C. K Yang, "Jitter Optimization Based on Phase-Locked Loop Design Parameters," IEEE JSSC, pp. 1375-1382, Nov. 2002.
14. 2 SRAM Cell," in IEEE IEDM, Dec. 2004, pp. 657-660.