Dynamic thermal clock skew compensation using tunable delay buffers

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 162-167

  Chakraborty, A ^a   Duraisami, K ^a   Sathanur, A ^a   Sithambaram, P ^a   Benini, L ^b   Macii, A ^a   Macii, E ^a   Poncino, M ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Clock skew; Clock tree; Temperature aware design methodology; Tunable delay buffers

Indexed keywords

BENCHMARKING; BUFFER CIRCUITS; DELAY CIRCUITS; PROBLEM SOLVING; TEMPERATURE DISTRIBUTION;

CLOCK SKEW; CLOCK TREES; TEMPERATURE AWARE DESIGN METHODOLOGY; TUNABLE DELAY BUFFERS;

LOGIC DESIGN;

EID: 34247232068     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165612     Document Type: Conference Paper

References (25)

1. K. Skadron et al., "Temperature-Aware Computer Systems: Opportunities and Challenges," IEEE Micro, Vol. 23, No. 6, Nov-Dec 2003, pp. 52-61.
2. S. Borkar et al., "Parameter Variation and Impact on Circuits and Microarchitectures," DAC'03: Design Automation Conference, 2003, Jun. 2003, pp. 338-342.
3. D. Brooks, M. Martonosi, "Dynamic thermal management for high-performance microprocessors" HPCA'01: High-Performance Computer Architecture, Jan. 2001, pp. 171-182.
4. J. Srinivasan, S. V. Adve, "Predictive Dynamic Thermal Management for Multimedia Applications," ICS'03: International Conference on Super-computing, June 2003.
5. K. Skadron, "Hybrid architectural dynamic thermal management," DATE'04: Design Automation and Test in Europe Conference, Feb. 2004, pp. 10-15.
6. Amir H. Ajami, Kaustav Banerjee, Massoud Pedram, "Modeling and Analysis of Nonuniform Substrate Temperature Effects on Global ULSI interconnects.", IEEE Transactions on CAD, Vol. 24, No. 6, June 2005, pp. 849-861.
7. M. Cho, S. Ahmed, D. Z. Pan, "TACO: Temperature Aware Clock-tree Optimization," ICCAD'05: International Conference on Computer-Aided Design, Nov. 2005, pp. 582-587.
8. A. Chakraborty et al.,"Thermal Resilient Bounded-Skew Clock Tree Optimization Methodology," DATE'06: Design Automation and Test in Europe, March 2006, pp. 832-837
9. J.-L. Tsai, D. Baik, C. C.-P. Chen, K. K. Saluja, "A Yield Improvement Methodology Using Pre- and Post-silicon Statistical Clock Scheduling," ICCAD'04: International Conference on Computer-Aided Design, Nov. 2004, pp. 611-618.
10. J.-L. Tsai, L. Zhang, C. Chen, "Statistical Timing Analysis Driven Post-Silicon-Tunable Clock-Tree Synthesis," ICCAD'05: International Conference on Computer-Aided Design, Nov. 2005, pp. 575-581.
11. R. S. Tsay, "Exact Zero Skew Clock Routing" ICCAD'91: International Conference on Computer-Aided Design, Nov. 1991, pp. 336-339.
12. T. H. Chao, Y-C.Hsu, J-M.Ho, K.D.Boese, A.B. Kahng, "Zero Skew Clock Routing with Minimum Wirelength," IEEE Transactions on Circuits and Systems II, Vol. 39, No. 11, Nov. 1992, pp. 799-814.
13. J. Cong, C. K. Koh, "Minimum-Cost Bounded-Skew Clock Routing," ISCAS'95: International Symposium on Circuits and Systems, May 1995, pp. 215-218.
14. D. J. H. Huang, A. B. Kahng, C.-H. A. Tsao, "On the Bounded-Skew Clock and Steiner Routing Problems," DAG'95: Design Automation Conference, Jun 1995, pp. 508-513.
15. Y.P. Chen, D.F. Wang, "An algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion," EDTC'96: European Design and Test Conference, Mar. 1996, pp. 230-236.
16. Jeng-Liang Tsai, Tsung-Hao Chen, Chen, C.C.-P, "Zero Skew Clock Tree Optimization with Buffer insertion/sizing and wire sizing.", IEEE Transactions on CAD, Vol. 23, No. 4, Jun 2004, pp. 565-572.
17. S. Tam et al., "Clock generation and distribution for the first IA-64 microprocessor," IEEE Journal of Solid-State Circuits, Vol. 35, No. 11, Jun 2000, pp. 1545-1552.
18. E. Takahashi, Y. Kasai, M. Murakawa, T. Higuchi, "A post-silicon clock timing adjustment using genetic algorithms," VLSI'03: Symposium on VLSI circuits, pp. 13-16.
19. A.DeHon, "In-System Timing Extraction and Control through Scan-Based, Test-Access Ports," ITC'94: International Test Conference 1994, Oct. 2004, pp. 350-359.
20. Y.Elboim, A.Kolodny, R.Ginosar, "A Clock Tuning Circuit for System-on-Chip," IEEE transactions on VLSI, Vol. 11, Issue 4, Aug. 2003, pp. 616-626.
21. S. Kaxiras, P. Xekalakis "4T-Decay Sensors: A New Class of Small, Fast, Robust, and Low-Power, Temperature/Leakage Sensors," ISLPED'04: International Symposium on Low Power Electronics and Design, Aug. 2004, pp. 108-113.
22. P. Chen, C.-C. Chen, C.-C. Tsai, W.-F. Lu "A Time-to-Digital- Converter-Based CMOS Smart Temperature Sensor," IEEE Journal of Solid-State Circuits, Vol. 40, No. 8, August 2005, pp. 1642-1648.
23. M. A. P. Pertijs "A CMOS Smart Temperature Sensor With a 3σ Inaccuracy of 0.5°C From 50°C to 120°C" IEEE Journal of Solid-State Circuits, Vol. 40, No. 2, February 2005, pp. 454-461.
24. K.Skadron et.al "Temperature-Aware Microarchitecture," ISCA '03: International Symposium on Computer Architecture, Jun 2003, pp. 2-13.
25. ftp://ftp.es.ele.tue.nl/pub/lp_solve