Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 1089-1097

  Chung, Kun Young ^a   Gupta, Sandeep K ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; DESIGN FOR TESTABILITY; ELECTRIC CLOCKS; ELECTRIC FAULT CURRENTS; FLIP FLOP CIRCUITS;

CLOCK RATES;

ELECTRONIC EQUIPMENT TESTING;

EID: 0142246862     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. D. Harris, "Skew-Tolerance Circuit Design", Academic Press, San Diego CA, 2001.
2. N.M. Abdulrazzaq, "Performance Testing of Data-Path Circuits", Ph.D. Dissertation, Department of Electrical Engineering - Systems, University of Southern California, 2001.
3. Kun Y. Chung and Sandeep K. Gupta, "Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing", Technical Report CENG 03-01, University of Southern California, 2003.
4. R. Gupta, R. Gupta, and M.A. Breuer, "The BALLAST Methodology for Structured Partial Scan Design", IEEE Trans. on Comptuers, 39(4), 1990.
5. N.M. Abdulrazzaq and Sandeep K. Gupta, "Test Generation for Path-Delay Faults in One-dimensional Iterative Logic Arrays", Proceedings IEEE International Test Conference, 2000.
6. nd Ed. Additon Wesley, 1992.