DFT-based SoC/VLSI IP protection and digital rights management platform

IEEE Transactions on Instrumentation and Measurement

Volumn 58, Issue 6, 2009, Pages 2026-2033

  Fan, Yu Cheng ^a   Shen, Jan Hung ^a  

^a NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

Author keywords

Design for test (DFT); Digital rights management (DRM); Intellectual property (IP) identification (ID); System on a chip (SoC); Very large scale integration (VLSI) design; Watermarking

Indexed keywords

DESIGN FOR TEST (DFT); DIGITAL RIGHTS MANAGEMENT (DRM); INTELLECTUAL PROPERTY (IP) IDENTIFICATION (ID); SYSTEM ON A CHIP (SOC); VERY LARGE SCALE INTEGRATION (VLSI) DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COPYRIGHTS; INTERNATIONAL LAW; INTERNET PROTOCOLS; LSI CIRCUITS; PROBABILITY DENSITY FUNCTION; PROGRAMMABLE LOGIC CONTROLLERS;

DESIGN;

EID: 67349104991     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2008.2006722     Document Type: Conference Paper

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