SeReCon: A trusted environment for SoPC design

Proceedings of International Conference on Dependability of Computer Systems, DepCoS - RELCOMEX 2008

Volumn , Issue , 2008, Pages 332-338

  Kȩpa, Krzysztof ^a   Morgan, Fearghal ^a   Kościuszkiewicz, Krzysztof ^a   Surmacz, Tomasz R ^b  

^a NATIONAL UNIVERSITY OF IRELAND   (Ireland)

^b WROCLAW UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION; DIGITAL COMMUNICATION SYSTEMS; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; INTELLECTUAL PROPERTY; MANAGEMENT; RELIABILITY; TECHNOLOGY; TELECOMMUNICATION;

DIGITAL COMMUNICATIONS; EMBEDDED-SYSTEM DESIGNS; HARDWARE AND SOFTWARE; INTELLECTUAL PROPERTY PROTECTION; INTERNATIONAL CONFERENCES; IP BLOCKS; PARTIAL RECONFIGURATION; POTENTIAL THREATS; RECONFIGURABLE COMPUTING; RECONFIGURABLE COMPUTING SYSTEMS; RECONFIGURATION CONTROLLER; RUN-TIME; RUN-TIME MANAGEMENT; SECURITY AND PRIVACY; TRUSTED COMPUTING BASE; TRUSTED ENVIRONMENT;

COMPUTER SYSTEMS;

EID: 51849130682     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DepCoS-RELCOMEX.2008.56     Document Type: Conference Paper

References (25)

1. Anderson R. J., Security engineering: A guide to building dependable distributed systems, John Wiley & Sons, Inc., New York, NY, USA, 2001. http://www.cl.cam.ac.uk/~rjal4/book.html.
2. FIPS PUB 140-3 Development. Security requirements for cryptographic modules. Technical report, U.S. Department of Commerce, 2007.
3. M. Huebner, L. Braun, J. Becker, C. Claus, and W. Stechele, "Physical configuration on-line visualization of Xilinx Virtex-II FPGAs". In VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on, pages 41-46, 2007.
4. T. Huffmire, B. Brotherton, G. Wang, T. Sherwood, R. Kastner, T. Levin, T. Nguyen, and C. Irvine, "Moats and drawbridges: An isolation primitive for reconfigurable hardware based systems", In IEEE Symposium on Security and Privacy, pages 281-295, 2007.
5. H. Kalte, M. Porrmann, "REPLICA2Pro: task relocation by bitstream manipulation in Virtex-II/Pro FPGAs", In CF '06: Proceedings of the 3rd conference on Computing frontiers, pages 403-412, New York, NY, USA, 2006. ACM Press.
6. K. Kepa, F. Morgan, K. Kosciuszkiewicz, and T. Surmacz, "SeReCon: a Secure Dynamic Partial Reconfiguration Controller", In IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2008.
7. Y. E. Krasteva, E. de la Torre, T. Riesgo, and Didier Joly, "Virtex II FPGA bitstream manipulation: Application to reconfiguration control systems", FPL '06. International Conference on Field Programmable Logic and Applications, pages 1-4, Aug. 2006.
8. D. Agrawal et al., "Trojan Detection using IC Fingerprinting", SP '07: Proceedings of the 2007 IEEE Symposium on Security and Privacy, IEEE Computer Society, 2007, 296-310.
9. A. Lesea, "IP security in FPGAs", Technical report, Xilinx, 2007.
10. M. McLean and J. More, "FPGA-based single chip cryptographic solution", Military Embedded Systems, 2007.
11. J.-B. Note and E. Rannaud, "From the bitstream to the netlist", Technical report, Departement d'informatique 'Ecole Normale Sup'erieure, September 2007.
12. K. Thompson, "Reflections on trusting trust", Commun. ACM, 27(8):761-763, 1984.
13. Xilinx, "Virtex-II Pro and Virtex-II Pro X platform FPGAs: Complete data sheet", Technical report, Xilinx, 2005.
14. Xilinx, "Virtex-II Pro user guide",Technical report, Xilinx, 2005.
15. Xilinx, "Virtex-4 Configuration Guide", Xilinx, Jan 2006.
16. Xilinx, "Virtex-5 Configuration User Guide", Technical report, Xilinx, 2007.
17. Xilinx, IP Center, http://www.xilinx.com/ipcenter/
18. G. E. Suh, C. W. O'Donnell, S. Devadas, "Aegis: A Single-Chip Secure Processor", IEEE Des. Test, IEEE Computer Society Press, 2007, 24, 570-580
19. Biba K.,"Integrity Considerations for Secure Computer Systems", Mitre Corp. MTR-3153, 1975
20. Bell D. E., LaPadula L., "Secure Computer Systems", ESD-TR-73-278, Mitre Corp., v I and II (1973), v III (1974).
21. B. Glas, A. Klimm, O. S. K. M. & J. Becker, "A System Architecture for Reconfigurable Trusted Platforms", DATE, 2008.
22. T. Guneysu, B. Moller, C. Paar, "Dynamic Intellectual Property Protection for Reconfigurable Devices", Field Programmable Technology, 2007. FPT 2007. IEEE International Conference on, 2007.
23. S. Drimer, "Authentication of FPGA bitstreams: Why and how" Workshop on Applied Reconfigurable Computing, Springer, 2007, 4419, 73-84.
24. Trusted Computing Group, http://www.trustedcomputinggroup.org/, 2003.
25. Smith S. W., Trusted Computing Platforms Design and Applications, Springer, 2005.