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Volumn , Issue , 2008, Pages 2645-2648

Intellectual property authentication by watermarking scan chain in design-for-testability flow

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS CONTROL; ARSENIC COMPOUNDS; AUTHENTICATION; DESIGN; DESIGN FOR TESTABILITY; INTELLECTUAL PROPERTY; INTERNET PROTOCOLS; NUCLEAR PROPULSION; SCANNING; TECHNICAL PRESENTATIONS; WATERMARKING;

EID: 51749119655     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4542000     Document Type: Conference Paper
Times cited : (24)

References (12)
  • 2
    • 0035472848 scopus 로고    scopus 로고
    • Constraint-Based Watermarking Techniques for Design IP Protection
    • Oct
    • A. B. Kahng et al., "Constraint-Based Watermarking Techniques for Design IP Protection" IEEE Trans. on CAD, vol. 20. no. 10, Oct. 2001, pp. 1236-1252.
    • (2001) IEEE Trans. on CAD , vol.20 , Issue.10 , pp. 1236-1252
    • Kahng, A.B.1
  • 4
    • 0032320166 scopus 로고    scopus 로고
    • Intellectual property protection by watermarking combinational logic synthesis solutions
    • San Jose, California, USA, Nov
    • D. Kirovski, Y.-Y. Wwang, M. Potkonjak, and J. Cong, "Intellectual property protection by watermarking combinational logic synthesis solutions," in Proc. IEEE/ACM Int. Conf. on CAD, San Jose, California, USA, Nov 1998, pp.194-198.
    • (1998) Proc. IEEE/ACM Int. Conf. on CAD , pp. 194-198
    • Kirovski, D.1    Wwang, Y.-Y.2    Potkonjak, M.3    Cong, J.4
  • 5
    • 34249810821 scopus 로고    scopus 로고
    • Stego-signature at logic synthesis level for digital design IP protection
    • Kos, Greece, May
    • A. Cui and C. H. Chang, "Stego-signature at logic synthesis level for digital design IP protection", in Proc. IEEE Int. Symp. on Circuits and Syst., Kos, Greece, May 2006, pp. 4611-4614.
    • (2006) Proc. IEEE Int. Symp. on Circuits and Syst , pp. 4611-4614
    • Cui, A.1    Chang, C.H.2
  • 6
    • 51749113297 scopus 로고    scopus 로고
    • Intellectual Property Protection using Watermarking Partial Scan Chains for Sequential Logic Test Generation
    • Nov
    • D. Kirovski, and M. Potkonjak, "Intellectual Property Protection using Watermarking Partial Scan Chains for Sequential Logic Test Generation", in Proc. IEEE High Level Design, Verification, and Test Conf., Nov. 1998.
    • (1998) Proc. IEEE High Level Design, Verification, and Test Conf
    • Kirovski, D.1    Potkonjak, M.2
  • 8
    • 0141829122 scopus 로고    scopus 로고
    • Watermarking for Intellectual Property Protection
    • Sept
    • Y. C. Fan, and H. W. Tsao, "Watermarking for Intellectual Property Protection", IEE Electronics Lett., vol. 39, no.18, Sept. 2003, 1316 - 1318.
    • (2003) IEE Electronics Lett , vol.39 , Issue.18 , pp. 1316-1318
    • Fan, Y.C.1    Tsao, H.W.2
  • 10
    • 0003380966 scopus 로고
    • Optimal Sequencing of Scan Registers
    • Baltimore, USA, Sept
    • S. Narayanan, C. Njinda and M. Breuer, "Optimal Sequencing of Scan Registers", in Proc. IEEE Int. Test Conf., Baltimore, USA, Sept. 1992, pp. 293-302.
    • (1992) Proc. IEEE Int. Test Conf , pp. 293-302
    • Narayanan, S.1    Njinda, C.2    Breuer, M.3
  • 11
    • 0001321331 scopus 로고    scopus 로고
    • Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application
    • Dec
    • V. Dabholkar, S. Chakravarty, I. Pomeranz and S.M. Reddy, "Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application," IEEE Trans. on CAD, vol. 17, no. 12, Dec. 1998, pp. 1325-1333.
    • (1998) IEEE Trans. on CAD , vol.17 , Issue.12 , pp. 1325-1333
    • Dabholkar, V.1    Chakravarty, S.2    Pomeranz, I.3    Reddy, S.M.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.