IP protection for VLSI designs via watermarking of routes

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 406-410

  Narayan, N ^a   Newbould, R D ^a   Carothers, J D ^a   Rodriguez, J J ^a   Holman, W T ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ARRAYS; INTEGRATED CIRCUIT LAYOUT; INTELLECTUAL PROPERTY; OPERATIONAL AMPLIFIERS; SECURITY OF DATA; TRANSISTORS; VLSI CIRCUITS;

ANALOG DESIGN; DIGITAL DESIGN; INTELLECTUAL PROPERTY PROTECTION; MIXED-SIGNAL DESIGN; STANDARD CELL;

DIGITAL WATERMARKING;

EID: 0034771122     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. The MCG autorouter for multichip modules
2. Watermarking layout topologies
3. Low level watermarking of VLSI designs for intellectual property protection
4. Watermarking of standard-cell feedthroughs in mixed-signal design
5. Placement watermarking of standard-cell designs
6. Mixed signal design watermarking for IP protection