Testing-based watermarking techniques for intellectual-property identification in SOC design

IEEE Transactions on Instrumentation and Measurement

Volumn 57, Issue 3, 2008, Pages 467-479

  Fan, Yu Cheng ^a  

^a NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

Author keywords

Design for test (DFT); Intellectual property (IP) identification; System on a chip (SOC); Very large scale integration (VLSI) design; Watermarking

Indexed keywords

DESIGN FOR TESTABILITY; ELECTRONIC DOCUMENT IDENTIFICATION SYSTEMS; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

INTELLECTUAL-PROPERTY (IP) IDENTIFICATION; SYSTEM-ON-A-CHIP (SOC); WATERMARK-GENERATING CIRCUIT;

DIGITAL WATERMARKING;

EID: 40549130402     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2007.911623     Document Type: Article

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