Testing based SoC/VLSI IP identification and protection platform

Conference Record - IEEE Instrumentation and Measurement Technology Conference

Volumn , Issue , 2007, Pages

  Fan, Yu Cheng ^a   Chiang, Arvin ^a   Sung, Da Cheng ^b   Chi, Tsung Chen ^a   Jiang, Jiyin Chang ^a   Hsieh, Yin Te ^a   Shen, Jan Hung ^a  

^a NATIONAL TAIPEI UNIVERSITY OF TECHNOLOGY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Intellectual property (IP); IP identification; IP protection; SoC VLSI design; Testing

Indexed keywords

IDENTIFICATION (CONTROL SYSTEMS); INTELLECTUAL PROPERTY; NETWORK ROUTING;

IP IDENTIFICATION; IP PROTECTION; VLSI DESIGN;

VLSI CIRCUITS;

EID: 34648813032     PISSN: 10915281     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/imtc.2007.379375     Document Type: Conference Paper

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