IP watermarking using incremental technology mapping at logic synthesis level

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 9, 2008, Pages 1565-1570

  Cui, Aijiao ^a,b   Chang, Chip Hong ^a,b   Tahar, Sofiène ^a,c  

^a IEEE

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

Digital watermarking; Incremental technology mapping; Intellectual property (IP) protection (IPP); Logic synthesis

Indexed keywords

COMPUTER NETWORKS; CONFORMAL MAPPING; DESIGN; DIGITAL WATERMARKING; INTERNET PROTOCOLS; SUSTAINABLE DEVELOPMENT;

INCREMENTAL TECHNOLOGY MAPPING; INTELLECTUAL PROPERTY (IP) PROTECTION (IPP); LOGIC SYNTHESIS; RE-MAPPING;

PAPERMAKING;

EID: 50549086060     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.927732     Document Type: Article

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