An Area-Saving Decoder Structure for ROMs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 4, 2003, Pages 581-589

  Wang, Chua Chin ^a   Hsueh, Ya Hsin ^a   Chen, Ying Pei ^b  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^b EMPIA Technology Inc   (Taiwan)

Author keywords

Area saving; Natural encoding; P+implant; Ready only memory (ROM) decoder; Three dimensional decoding

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; ENCODING (SYMBOLS); ENERGY UTILIZATION;

DECODER STRUCTURE;

ROM;

EID: 0141862189     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.816134     Document Type: Article

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