A Low-Power Charge-Recycling ROM Architecture

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 4, 2003, Pages 590-600

  Yang, Byung Do ^a   Kim, Lee Sup ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Bit line; Charge recycling; Low power design; Read only memory (ROM); Very large scale integration (VLSI) design; Word line

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ENERGY UTILIZATION; VLSI CIRCUITS;

CHARGE RECYCLING;

ROM;

EID: 0141527492     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.816138     Document Type: Article

References (8)

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