Conforming block inversion for low power memory

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 1, 2002, Pages 15-19

  Chang, You Sung ^a,b   Kyung, Chong Min ^a,b  

^a IEEE   (South Korea)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Dynamic logic circuit; Low power design; Low power dissipation; Memory; Switching activity

Indexed keywords

LOW-POWER DESIGNS; POWER CONSUMPTION;

COMPUTER SIMULATION; ENERGY DISSIPATION; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; POWER CONTROL; SWITCHING;

DATA STORAGE EQUIPMENT;

EID: 0036476969     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.988726     Document Type: Article

References (10)

1. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
2. Customization of a CISC core for low power applications
3. A single bitline cross-point cell activation architecture for ultra low power SRAMS
4. A charge recycle refresh for Gb-scale DRAMs in file applications
5. A 1-V 1-Mb SRAM for portable equipment
6. Techniques to reduce power in fast wide memories
7. A low-power chipset for a portable multimedia I/O terminal
8. Bus-invert coding for low-power I/O
9. Issues in the design of the marcia internal cache
10. Cache designs with partial address matching