A low-power ROM using charge recycling and charge sharing techniques

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 4, 2003, Pages 641-653

  Yang, Byung Do ^a   Kim, Lee Sup ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Bitline; Charge recycling; Charge sharing; Low power design; Predecoder line; ROM; VLSI design; Wordline

Indexed keywords

CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS; VOLTAGE CONTROL;

CHARGE RECYCLING PREDECODER; CHARGE RECYCLING WORDLINE DECODER; CHARGE SHARING BITLINE; LOW-POWER ROM; VLSI DESIGN;

ROM;

EID: 0037390642     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.809516     Document Type: Article

References (8)

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5. ____, "A Low-power ROM using charge recycling and charge sharing," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 108-109.
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