Analysis and optimization of power grids

IEEE Design and Test of Computers

Volumn 20, Issue 3, 2003, Pages 7-15

  Sapatnekar, Sachin S ^a   Su, Haihua ^b  

^a University of Minnesota   (United States)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT DENSITY; DIFFERENTIAL EQUATIONS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; ELECTROMIGRATION; MATRIX ALGEBRA; SPURIOUS SIGNAL NOISE; VECTORS;

CLOCK NETWORKS;

POWER SUPPLY CIRCUITS;

EID: 0038382898     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1198680     Document Type: Review

References (24)

1. L. Polka et al., "Package-Level Interconnect Design for Optimum Electrical Performance," Intel Technology J., Quarters, Aug. 2000; http://www.intel.com/technology/itj/q32000/articles/art_3.htm.
2. H.H. Chen and D.D. Ling, "Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design," Proc. 34th Design Automation Conf. (DAC 97), ACM Press, 1997, pp. 638-643.
3. A. Dharchowdhury et al., "Design and Analysis of Power Distribution Networks in PowerPC Microprocessors," Proc. 35th Design Automation Conf. (DAC 98), ACM Press, 1998, pp. 738-743.
4. L.T. Pillage, R.A. Rohrer, and C. Visweswariah, Electronic and System Simulation Methods, McGraw-Hill, 1995.
5. A. Devgan, H. Ji, and W. Dal, "How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K," Proc. Int'l Conf. Computer-Aided Design (ICCAD 00), ACM Press, 2000, pp. 150-155.
6. M. Zhao et al., "Hierarchical Analysis of Power Distribution Networks," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 2, Feb. 2002, pp. 159-168.
7. J. Kozhaya, S.R. Nassif, and F.N. Najm, "A Multigridlike Technique for Power Grid Analysis," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 10, Oct. 2002, pp. 1148-1160.
8. H. Su, K.H. Gala, and S.S. Sapatnekar, "Fast Analysis and Optimization of Power/Ground Networks," Proc. Int'l Conf. Computer-Aided Design (ICCAD 00), ACM Press, 2000, pp. 477-480.
9. Y. Cao et al., "HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodellng Engine for RLKC Power Delivery," Proc. 39th Design Automation Conf. (DAC 02), ACM Press, 2002, pp. 379-384.
10. H. Su, S.S. Sapatnekar, and S.R. Nassif, "An Algorithm for Optimal Decoupling Capacitor Sizing and Placement for Standard Cell Layouts," Proc. Int'l Symp. Physical Design (ISPD 02), ACM Press, 2002, pp. 68-73.
11. A.R. Conn, R.A. Haring, and C. Visweswariah, "Noise, Considerations In Circuit Optimization," Proc. Int'l Conf. Computer-Aided Design (ICCAD 98), ACM Press, 1998, pp. 220-227.
12. J.C. Shah et al., "An Algorithm for Simulating Power/Ground Networks Using Padé Approximants and its Symbolic Implementation," IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, vol. 45, no. 10, Oct. 1998, pp. 1372-1382.
13. H. Su et al., "Congestion-Driven Codesign of Power and Signal Networks," Proc. 39th Design Automation Conf. (DAC 02), ACM Press, 2002, pp. 64-69.
14. X.-D. Tan et al., "Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmlngs," Proc. 36th Design Automation Conf. (DAC 99), ACM Press, 1999, pp. 78-83.
15. S.W. Director and R.A. Rohrer, "The Generalized Adjoint Network and Network Sensitivities," IEEE Trans. Circuit Theory," vol. 16, no. 8, Aug. 1969, pp. 318-323.
16. S. Chowdhury, "Optimum Design of Reliable IC Power Networks Having General Graph Topologies," Proc. 26th Design Automation Conf. (DAC 89), ACM Press, 1989, pp. 787-790.
17. S. Zhao, K. Roy, and C.-K. Koh, "Decoupling Capacitance Allocation for Power Supply Noise Suppression," Proc. Int'l Symp. Physical Design (ISPD 01), ACM Press, 2001, pp. 66-71.
18. C. Zhu, R.H. Byrd, and J. Nocedal, LBFGS-B: Fortran Subroutines for Large-Scale Bound Constrained Optimization, Report NAM-11, EECS Dept., Northwestern Univ., Evanston, Ill., 1994.
19. G. Bal, S. Bobba, and I.N. Hajj, "Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, 2001, pp. 295-300.
20. L.H. Chen, M. Marek-Sadowska, and F. Brewer, "Coping with Buffer Delay Change due to Power and Ground Noise," Proc. 39th Design Automation Conf. (DAC 02), ACM Press, 2002, pp. 860-865.
21. R. Saleh et al., "Clock Skew Verification in the Presence of IR-Drop In the Power Distribution Network," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 6, June 2000, pp. 635-644.
22. B. Stanisic, R.A. Rutenbar, and LR. Carley, Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs, Kluwer Academic, 1996.
23. P. Saxena and S. Gupta, "Shield Count Minimization In Congested Regions," Proc. Int'l Symp. Physical Design (ISPD 02), ACM Press, 2002, pp. 78-84.
24. J.D. Ma and L. He, "Toward Global Routing with RLC Crosstalk Constraints," Proc. 39th Design Automation Conf. (DAC 02), ACM Press, 2002, pp. 669-672.