Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 811-816

  Popovich, Mikhail ^a   Friedman, Eby G ^a   Secareanu, Radu M ^b   Hartin, Oliri L ^b  

^a University of Rochester   (United States)

^b MMSTL   (United States)

Author keywords

Decoupling capacitors; Power distribution grids; Power distribution systems; Power noise

Indexed keywords

AD HOC APPROACH; ANALYTIC SOLUTIONS; COMPUTER-AIDED DESIGN; CURRENT LOADS; CURRENT TECHNOLOGIES; DECOUPLING CAPACITORS; DISTRIBUTED SYSTEMS; EFFICIENT SOLUTIONS; FUTURE TECHNOLOGIES; INTERNATIONAL CONFERENCES; NANO SCALING; ON CHIPS; ON-CHIP DECOUPLING; ON-CHIP DECOUPLING CAPACITORS; PARASITIC IMPEDANCE; PARASITIC RESISTANCES; POWER DELIVERY; POWER DISTRIBUTION GRIDS; POWER DISTRIBUTION SYSTEMS; POWER DISTRIBUTIONS; POWER NOISE; POWER-SUPPLY NOISE; SIGNAL-INTEGRITY; SIMULATION RESULTS; TECHNOLOGY CONSTRAINTS; TYPICAL VALUES; WHITE SPACE; WORST-CASE ERRORS;

CAPACITANCE; CAPACITORS; DESIGN; DIELECTRIC DEVICES; ELECTRIC CONVERTERS; ELECTRIC CURRENTS; ELECTRIC EQUIPMENT; ELECTRIC POWER DISTRIBUTION; ELECTRIC POWER TRANSMISSION; ENERGY STORAGE; RELIABILITY; SIGNAL PROCESSING; TECHNOLOGY;

PAPER CAPACITORS;

EID: 50249109580     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397365     Document Type: Conference Paper

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