Automatic test pattern generation for interconnect open defects

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2008, Pages 181-186

  Spinner, Stefan ^a   Polian, Ilia ^a   Engelke, Piet ^a   Becker, Bernd ^a   Keim, Martin ^b   Cheng, Wu Tung ^b  

^a UNIVERSITY OF FREIBURG   (Germany)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

ATPG; Interconnect opens; Open via defects

Indexed keywords

CURVE FITTING; DEFECTS; HELIUM; PARAMETER EXTRACTION;

ATPG; INTERCONNECT OPENS; OPEN-VIA DEFECTS; VLSI TESTS;

AUTOMATIC TEST PATTERN GENERATION;

EID: 51449094983     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2008.30     Document Type: Conference Paper

References (18)

1. R. Blish, T. Dellin, S. Huther, M. Johnson, J. Maiz, B. Likins, N. Lycoudes. J. McPherson, Y. Peng. C. Peridier, A. Preussger, G. Propkop, and L. Tullos. Critical Reliability Challenges for the International Technology Roadmap for Semiconductors (ITRS), 2003.
2. Y. Sato, I. Yamazaki, H. Yamanaka, T. Ikeda, and M. Takakura. A persistent diagnostic technique for unstable defects. In Int'l Test Conf., pages 242-249, 2002.
3. B. Koenemann. Test in the era of "What you see is NOT what you get". In Int'l Test Conf., page 12, 2004. (Keynote address).
4. S.P. Murarka. I.V. Verner, and R.J. Gutmann. Copper-Fundamental Mechanisms for Microelectronis Applications. John Wiley & Sons, 2000.
5. V.H. Champac, R. Rodriguez-Montanes, J. A. Segura, J. Figueras, and J.A. Rubio. Fault modelling of gate oxide short, floating gate and bridging failures in CMOS circuits. In European Test Conf., pages 143-148, 1991.
6. M. Renovell and G. Cambon. Electrical analysis and modeling of floating-gate fault. IEEE Trans. on CAD, 11(11): 1450-1458, 1992.
7. S. Rafiq, A. Ivanov, S. Tabatabaei, and M. Renovell. Testing for floating gates defects in CMOS circuits. In Asian Test Svmp., pages 228-236, 1998.
8. D. Arumí, Rodríguez-Montañés, and J. Figueras. Experimental characterization of CMOS interconnect open defects. IEEE Trans. on CAD. 27(1):123-136, 2008.
9. H. Konuk. Fault simulation of interconnect opens in digital CMOS circuits. In Int'l Conf. on CAD, pages 548-554, 1997.
10. S. Venkataraman and S.B. Drummonds. A technique for logic fault diagnosis of interconnect open defects. In VLSI Test Symp., pages 313-318, 2000.
11. S.M. Reddy. I. Pomeranz, H. Tang, S. Kajihara, and K. Kinoshita. On testing of interconnect open detects in combinational logic circuits with stems of large fanout. In Int'l Test Conf., pages 83-89, 2002.
12. W. Zou, W.T. Cheng, and S.M. Reddy. Interconnect open defect diagnosis with physical information. In Asian Test Symp., pages 203-208, 2006.
13. H. Takahashi, Y. Higami, S. Kadoyama, T. Aikyo, Y. Takamatsu, K. Yamazaki, H. Yotsuyanagi, and M. Hashizume. Clues for modeling and diagnosing open faults with considering adjacent lines. In Asian Test Symp., pages 39-44, 2007.
14. R. Rodriguez-Montanes, D. Arumi, J. Figueras. S. Einchenberger, C. Hora B. Kruseman, M. Lousberg, and A.K. Majhi. Diagnosis of full open defects in interconnecting lines. In VLSI Test Symp., pages 158-166, 2007.
15. N. Jarwala and C.W. Yau. A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects. In Int'l Test Conf., pages 63-70, 1989.
16. J.G. Deshayes and G.D. Robinson. Interconnect testing of boards with partial boundary scan. In Int'l Test Conf., pages 572-581, 1990.
17. R. Gómez, A. Girón, and V. Champac. Test of interconnection opens considering coupling signals. In IEEE Defect and Fault Tolerance Symp., pages 247-255, 2005.
18. S. Spinner, J. Jiang, I. Polian, P. Engelke, and B. Becker. Simulating open-via defects. In Asian Test Symp., pages 265-270, 2007.