Test of interconnection opens considering coupling signals

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2005, Pages 247-255

  Gomez, Roberto ^a   Giron, Alejandro ^a   Champac, Victor ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COUPLED CIRCUITS; DEFECTS; INFORMATION ANALYSIS; MATHEMATICAL MODELS;

COUPLING SIGNALS; LAYOUT INFORMATION;

OPTICAL INTERCONNECTS;

EID: 28444433361     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

1. W. Maly, P.K. Nag and P. Nigh,"Terting Oriented Analysis of CMOS IC's with Opens", Proc. Int. Conf. on Computer-Aided Design, pp. 344-347, 1988.
2. C. L. Henderson, J. M.Soden and C. F. Hawkins, "The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits", International Test Conference, pp. 302-310, 1991.
3. Hua Xue, Chennian Di, and J.A.G. Jess, "Probability Analysis for CMOS Floating Gate Faults", European Design and Test Conference, pp. 443-448. 1994.
4. D.B.I. Feltham, W. Maly, "Physically Realistic Fault Models for Analog CMOS Neural Networks", IFEE Journal of Solid-State Circuits, Sept. 1991.
5. K.M. Thompson, "Intel and the myths of test", In the Keynote Address of ITC, 1995.
6. S. Johnson, "Residual Charge on the Faulty Floating Gate MOS Transistors", International Test Conference, pp. 555-561, 1994.
7. Haluk Konuk, F. Joel Ferguson, "An unexpected factor int testing for CMOS Opens: The die surface", IEEE VLSI Test Symposium, 1996.
8. Haluk Konuk, F. Joel Ferguson, "Oscillation and Sequential Behavior Caused by Opens in the Routing in Digital CMOS Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 17, No. 11, pp. 1200-1210, November 1998.
9. Haluk Konuk, "Fault Simulation of Interconnect Opens in Digital CMOS Circuits", International Conference in Computer Aided-Dcsign, 1997.
10. DDQ Testing of CMOS Opens: An experimental Study", International Test Conference, pp. 479-489, 1995.
11. R. Makki, S. Su, T. Nagle, "Transient Power Supply Current Testing of Digital CMOS Circuits", International Test Conference, pp. 892-901, 1995
12. DDQ Testing", IEEE Transactions on Computer-Aided Design, Vol. 13, No. 3, pp. 359-369, March 1994.
13. Daniel Arumi, Rosa Rodriguez-Montaes and Joan Figueras, "Defective Behaviours of Resistive Opens in Interconnect Lines", European Test Symposium, pp. 28-33, May 2005.
14. Shalini Ghosh, F. Joel Ferguson, "Estimating Detection Probability of Interconnect Opens using Stuckat Test", GLSVLSI'04, pp. 254-259, April 2004.
15. Charles F. Hawkins, Jerry M. Soden, Alan W. Righter, F. Joel Ferguson, "Defect Classes- An Overdue Paradigm for CMOS IC Testing", International Test Conference, pp. 413-425, 1994.
16. W. Moore, G. Gronthoud, K Baker, M. Lousberg, "Delay-Fault Testing and Defects in Deep Sub-micron IC's-Doee Critical Resistance really mean anything?", International Test Conference, 2000.
17. Antonio Zenteno, Victor H. Champac, "Detectability Conditions of Full Opens in the Interconnections", Journal of Electronic Testing: Theory and Applications, Vol 17, pp 85-95, 2001.
18. M. Renovell and G. Cambon, "Electrical Analysis and Modeling of Floating-Gate Fault", IEEE Transactions on Computer-Aided Design, Vol. 11, No. 11, pp. 1450-1458, November 1992.
19. K. Rahmat, O. S. Nakagawa, S-Y. Oh, J. Moll and W. T. Lynch, "A Scaling Scheme for Interconnect in Deep-Submicron Processes", HP Labs, HPL-95-123, Tech. Rep., Nov. 1995.
20. SYNOPSIS, "TetraMAX ATPG User Guide", Version 2001.08, August 2001.
21. CADENCE, "Custom IC Design Tools", Vervion 4.4.6, 2000.
22. Alejandro Giron, "An Strategy to Test Interconnection Opens Considering Coupling Capacitances", MsC Thesis-National Institute for Astrophysics, Optics and Electronics, 2003.