Tranlsition test on ultraSPARC TM T2 M-icroprocessor

Proceedings - International Test Conference

Volumn , Issue , 2008, Pages

  Chen, Liang Chi ^a   Dickinson, Paul ^a   Mantri, Prasad ^a   Gala, Murali ^a   Dahlgren, Peter ^a   Bhattacharya, Subhra ^a   Caty, Olivier ^a   Woodling, Kevin ^a   Ziaja, Thomas ^a   Curwen, David ^a   Yee, Wendy ^a   Su, Ellen ^a   Gu, Guixiang ^a   Nguyen, Tim ^a  

^a Sun Microsystem   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ESSENTIAL PATTERNS; PROCESSOR CORES; SILICON DEBUG; TEST DEVELOPMENT; TEST SEQUENCE; TRANSITION TESTS; ULTRASPARC;

TESTING;

EID: 67249105298     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2008.4700599     Document Type: Conference Paper

References (18)

1. C-W. Tseng and E. J. McCluskey. "Multiple Output Propagation Transition Fault Test", Proc. Int'l Test Conf., 2001, pp.358-366.
2. P. Nigh, W. Needham, K. Butler, et al., "An Experimental Study Comparing the Relative Effectiveness of Functional, Scan, Iddq, and Delay-Fault Testing,", Proc. VLSI Test Symp., 1997, pp. 459-464.
3. J. Saxena, K. M. Butler, J. Gatt, et al., "Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges", Proc. Int'l Test Conf., 2002, pp. 1120- 1129.
4. R.S. Fetherston, I.P. Shaik, and S.C. Ma, "Testability features of AMD-K6 microprocessor", Proc. Int'l Test Conf., 1997, pp.406-413.
5. C. Pyron, M. Alexander, J. Golab, et al., "DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor", Proc. Int'l Test Conf., 1999, pp.137- 146.
6. D. Belete, A. Razdan, W. Schwarz, et al., "Use of DFT techniques in speed grading a 1 GHz+ microprocessor", Proc. Int'l Test Conf., 2002, pp.1111-1119.
7. Y. -S. Chang, S. Chakravarty, H. Hoang, et al., "Transition test for high performance microprocessors", Proc. VLSI Test Symp., 2005, pp. 29-34.
8. V. Iyengar, T. Yokota, K. Yamada, et al., "At-Speed Structural Test For High-Performance ASICs", Proc. Int'l Test Conf., 2006, pp. 1-10.
9. R. Molyneaux, T. Ziaja; H. Kim, et al., "Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip", Proc. Int'l Test Conf., 2007, pp. 1-8.
10. N. Tendolkar, R. Molyneaux, C. Pyron, and R. Raina, "At-speed testing of delay faults for Motorola's MPC7400, a PowerPC TM microprocessor", Proc. VLSI Test Symp., 2000, pp.3-8.
11. N. Tendolkar, R. Raina, W. Woltenberg, et al., "Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC/spl trade/ instruction set architecture", Proc. VLSI Test Symp., 2002, pp.3-8.
12. R. Raina, R. Bailey, D. Belete, et al., "DFT advances in Motorola's Next-Generation 74xx PowerPC microprocessor", Proc. Int'l Test Conf., 2000, pp.131-140.
13. J. Zeng, M. Abadir, G. Vandling, et al., "On correlating structural tests with functional tests for speedbinning of high performance design", Proc. Int'l Test Conf., 2004, pp.31-37.
14. U.M. Nawathe, M. Hassan, L. Warriner, et al., "An 8-Core 64-Thread 64b Power-Efficient SPARC SoC", Proc. Int'l Solid-State Circuits Conf., 2007, pp. 108-109.
15. I. Parulkar, T. Ziaja, R. Pendurkar, et al., "A scalable, low cost design-for-test architect", Proc. Int'l Test Conf., 2002 , pp. 726 - 735.
16. X. Lin, R. Press, J. Rajski, et al., "High-Frequency, at speed scan testing", IEEE Design & Test of Computers, Sep 2003, pp. 17-25.
17. V. Vorisek, B. Swanson, K.-H. Tsai, et al., "Improved handling of false and multicycle paths in ATPG", Proc. VLSI Test Symp., 2006.
18. D. Goswami, K.-H. Tsai, M. Kassab, et al., "At- Speed Testing with Timing Exceptions and Constraints- Case Studies", Proc. Asia Test Symp., 2006, pp. 153 - 162.