An 8-core 64-thread 64b power-efficient SPARC SOC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 108-110

  Mawathe, Umesh Gajanan ^a   Hassan, Mahmudul ^a   Warriner, Lynn ^a   Yen, King ^a   Upputuri, Bharat ^a   Greenhill, David ^a   Kumar, Ashok ^a   Park, Heechoul ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CACHE MEMORY; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; ETHERNET; TRANSISTORS;

POWER EFFICIENT CHIPS; TRANSISTOR CHIPS;

CHIP SCALE PACKAGES;

EID: 34548816981     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373611     Document Type: Conference Paper

References (2)

1. Greg Grohoski, et al., "Niagara2: A Highly Threaded Server-on-a-Chip," Hot Chips Symposium, Aug., 2006.
2. Ana Sonia, Leon, et al., "A Power-Efficient High-Throughput 32-Thread SPARC Processor," ISSCC Dig. Tech. Papers, pp. 98-99, Feb., 2006.