Use of DFT techniques in speed grading a 1GHz+ microprocessor

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 1111-1119

  Belete, Dawit ^a   Razdan, Ashutosh ^a   Schwarz, William ^a   Raina, Rajesh ^a   Hawkins, Christopher ^a   Morehead, Jeff ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC FREQUENCY MEASUREMENT; FAILURE ANALYSIS; INTERCONNECTION NETWORKS; LOGIC DESIGN; MICROELECTRONIC PROCESSING; MICROPROCESSOR CHIPS; SILICON ON INSULATOR TECHNOLOGY;

LOGIC BUILT-IN SELF TEST; PATH DELAY SCAN PATTERN; SPEED GRADING; TRANSITION FAULT;

DESIGN FOR TESTABILITY;

EID: 0036443322     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. D. Bearden, et al., "A 780 MHz PowerPC Microprocessor with Integrated L2 Cache," Proc. of IEEE Solid State Circuit Conf., Feb. 2000.
2. N. Iyengar, "A New PowerPC Microprocessor with AltiVec Technology," Microprocessor Forum, Session 2, Oct. 1999.
3. J. Alvarez, et al., "450 MHz PowerPC Microprocessor with Enhanced Instruction Set and Copper Interconnect," Proc. of IEEE Solid State Circuits Conf., Feb. 1999.
4. TM Microprocessor", Proc. of the IEEE Int'l Test Conf., pp. 137-146, Sept. 1999.
5. M. Abadir & R. Raina, "Design For Test Methodology for Motorola PowerPC Microprocessors," Proc. of IEEE Int'l Test Conference, pp., Sept. 1999.
6. C. Pyron, J. Prado, & J. Golab, "Next Generation PowerPC Microprocessor Test Strategy Improvements", Proc. of the IEEE Int'l Test Conf., pp. 414-423, 1997.
7. TM Microprocessor," Proc. Int'l Test Conf., pp. 76-83, 1994.
8. C. Hunter et al., "The PowerPC 603 Microprocessor: An Array Built-in Self Test Mechanism", IEEE Int'l Test Conference, pp. 388-394, 1994.