Improved handling of false and multicycle paths in ATPG

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 17-22

  Vorisek, Vlado ^a   Swanson, Bruce ^b   Tsai, Kun Han ^b   Goswami, Dhiraj ^b  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; ELECTRONIC EQUIPMENT; PRODUCT DEVELOPMENT; QUALITY CONTROL;

AUTOMATIC TEST PATTERN GENERATION (ATPG); ELECTRONIC DESIGN; STATIC TIMING ANALYSIS (STA);

MACHINE DESIGN;

EID: 33751094886     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.38     Document Type: Conference Paper

References (11)

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