On correlating structural tests with functional tests for speed binning of high performance design

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 31-37

  Zeng, J ^a   Abadir, M ^a   Vandling, G ^b   Wang, L ^c   Kolhatkar, A ^a   Abraham, J ^d  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INSTRUCTION SET ARCHITECTURE; SPEED BINNING; SPEED MEMORY TEST; STRUCTURAL PATTERNS;

CROSSTALK; DATA ACQUISITION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROGRAM DEBUGGING; VECTORS;

INTEGRATED CIRCUITS;

EID: 18144362154     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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