At-speed testing with timing exceptions and constraints -case studies

Proceedings of the Asian Test Symposium

Volumn 2006, Issue , 2006, Pages 153-159

  Goswami, Dhiraj ^a   Tsai, Kun Han ^a   Kassab, Mark ^a   Kobayashi, Takeo ^a   Rajski, Janusz ^a   Swanson, Bruce ^a   Walters, Darryl ^a   Sato, Yasuo ^b   Asaka, Toshiharu ^b   Aikyo, Takashi ^b  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

At speed test; False paths; Multicycle paths; Static timing analysis (STA); Synopsys design constraints (SDC); Timing constraints; Timing exceptions

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION (ATPG);

CONSTRAINT THEORY; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS;

ELECTRONIC EQUIPMENT TESTING;

EID: 33947648448     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2006.261014     Document Type: Conference Paper

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