ParallAX: An architecture for real-time physics

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2007, Pages 232-243

  Yeh, Thomas Y ^a   Faloutsos, Petros ^a   Patel, Sanjay J ^b   Reinman, Glenn ^a  

^a Department of Civil and Environmental Engineering   (United States)

^b AGEIA Technologies

Author keywords

Application specific processor; Chip multiprocessor; Interactive entertainment; Physics based animation; Real time physics; Stream processing

Indexed keywords

APPLICATION SPECIFIC PROCESSOR; INTERACTIVE ENTERTAINMENT; PHYSICS BASED ANIMATION; REAL-TIME PHYSICS; STREAM PROCESSING;

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; SENSITIVITY ANALYSIS;

INTERACTIVE COMPUTER SYSTEMS;

EID: 35348814920     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1250662.1250691     Document Type: Conference Paper

References (28)

1. HyperTransport 3.0 Spec. http://www.hypertransport.org/docs/tech/HT3pres. pdf.
2. PCIE Express Spec. http://www.pcisig.com/speciflcations/pciexpress/.
3. AGEIA. Physx product overview, www.ageia.com.
4. J. Andrews and N. Baker. Xbox 360 system architecture. In IEEE Computer Society, 2006.
5. David Baraff. Physically Based Modeling: Principals and Practice. SIGGRAPH Online Course Notes, 1997.
6. D. Chiou, P. Jain, S. Devadas, and L. Rudolph. Dyna-mic cache partitioning via columnization. In Proceedings of Design Automation Conference, 2000.
7. Open Dynamics Engine. http://www.ode.org/ode-latest-userguide.html.
8. Havok. http://www.havok.com/content/view/187/77.
9. J. Hennessy and D. Patterson. Computer Architecture a Quantitative Approach. Morgan Kaufmann Publishers, Inc., 1996.
10. P. Hofstee. Power efficient architecture and the cell processor. In HPCA11, 2005.
11. T Jakobsen. Advanced character physics using the fysix engine, www.gamasutra.com, 2001.
12. U. J. Kapasi, S. Rixner, W. J. Dally, B. Khailany, J. H. Ahn, P. Mattson, and J. D. Owens. Programmable stream processors. In IEEE Computer, 2003.
13. C. Kozyrakis and D. Patterson. Vector vs. superscalar and vliw architectures for embedded multimedia benchmarks. In Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, 2002.
14. C. Kozyrakis and D. Patterson. Overcoming the limitations of conventional vector processors. In 30th Annual International Symposium on Computer Architecture, 2003.
15. F. Labonte, P. Mattson, W. Thies, I. Buck, C. Kozyrakis, and M. Horowitz. The stream virtual machine. PACT, 2004.
16. P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hallberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner. Simics: A full system simulation platform. In IEEE Computer, Feb 2002.
17. M. Martin, D. Sorin, B. Beckmann, M. Marty, M. Xu, A. Alameldeen, K. Moore, M. Hill, and D. Wood. Multifacet's general execution-driven multiprocessor simulator (gems) toolset. In Computer Architecture New, Sep 2005.
18. M. Matthias, B. Heidelberger, M. Hennix, and J. Ratcliff. Position based dynamics. In Proceedings of the 3rd Workshop in Virtual Reality Interactions and Physical Simulation, 2006.
19. V. Moya, C. Gonzalex, J. Roca, A. Fernandez, and R. Espasa. Shader performance analysis on a modern gpu architecture. In Proceedings of the 38th annual ACM/IEEE international symposium on Microarchitecture, 2005.
20. M. Pharr and R. Fernando. GPU Gems 2. Pearson Education, 2005.
21. P. Ranganathan, S. V. Adve, and N.P. Jouppi. Reconfigurable caches and their application to media processing. In 27th Annual International Symposium on Computer Architecture, 2000.
22. P. Schmid and B. Topelt. Game over? core 2 duo knocks out athlon 64. http://www.tomshardware.com/2006/07/14/.
23. R. Sommefeldt. Nvidia, g80: Architecture and gpu analysis. http://www.beyond3d.com/reviews/nvidia/g80-arch/.
24. V. Soteriou, N. Eisley, H. Wang, B. Li, and L. Peh. Polaris: A system-level roadmap for on-chip interconnection networks. In Proceedings of the 24th International Conference on Computer Design, 2006.
25. H. S. Stone, J. Turek, and J. L. Wolf. Optimal partitioning of cache memory. In IEEE transactions on Computers, 1992.
26. M. Taiji. Mdgrape-3 chip: a 165 gfiops application specific lsi for molecular dynamics simulations. In Hot Chips 16, 2004.
27. T. Y. Yeh, P. Faloutsos, and G. Reinman. Enabling real-time physics simulation in future interactive entertainment. In ACMc SIGGRAPH Video Game Symposium, 2006.
28. T. Y. Yeh and G. Reinman. Fast and fair: Data-stream quality of service. In International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, 2005.