Universal mechanisms for data-parallel architectures

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2003-January, Issue , 2003, Pages 303-314

  Karthikeyan Sankaralingam, ^a   Keckler, S W ^a   Mark, W R ^a   Burger, D ^a  

^a University of Texas at Austin   (United States)

Author keywords

Application software; Communication system control; Computational modeling; Computer architecture; Digital signal processing chips; Engines; Graphics; Hardware; Laboratories; Reconfigurable architectures

Indexed keywords

APPLICATION PROGRAMS; COMPUTER ARCHITECTURE; COMPUTER CONTROL SYSTEMS; COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; ENGINES; LABORATORIES; MEMORY ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; PARALLEL PROGRAMMING; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; SIGNAL PROCESSING;

BASE-LINE ARCHITECTURE; COMMUNICATION SYSTEM CONTROL; COMPUTATIONAL INTENSITY; COMPUTATIONAL MODEL; DATA-PARALLEL APPLICATIONS; DATA-PARALLEL ARCHITECTURES; DIGITAL SIGNAL PROCESSING CHIPS; GRAPHICS;

PARALLEL ARCHITECTURES;

EID: 84944402628     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2003.1253204     Document Type: Conference Paper

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