Low-leakage and low-power implementation of high-speed 65nm logic gates

2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC

Volumn , Issue , 2008, Pages

  Wu, Tsung Yi ^a   Lu, Liang Ying ^a   Liang, Cheng Hsun ^a  

^a NATIONAL CHANGHUA UNIVERSITY OF EDUCATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BATTERIES; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; LOGIC GATES; PROGRAM COMPILERS;

65NM GATES; CMOS GATES; DYNAMIC POWER; DYNAMIC POWER CONSUMPTION; FULL SWINGS; HIGH-SPEED; LOW-POWER; NEW STRUCTURES; PASS-TRANSISTOR LOGIC; POWER REDUCTIONS; PROPAGATION DELAYS; SHORTER DELAYS; STANDARD CELLS; TRANSISTOR COUNTS;

SOLID STATE DEVICES;

EID: 63249126113     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EDSSC.2008.4760641     Document Type: Conference Paper

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