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Volumn 2006, Issue , 2006, Pages 565-569

Analysis and optimization of gate leakage current of power gating circuits

Author keywords

[No Author keywords available]

Indexed keywords

MOSFET DEVICES; OPTIMIZATION; POWER SUPPLY CIRCUITS; THRESHOLD VOLTAGE;

EID: 33748617571     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118434     Document Type: Conference Paper
Times cited : (14)

References (12)
  • 1
    • 0031635596 scopus 로고    scopus 로고
    • Design and optimization of low voltage high performance dual threshold CMOS circuits
    • June
    • L. Wei, Z. Chen, M. Johnson, K. Roy, and V. De, "Design and optimization of low voltage high performance dual threshold CMOS circuits," Proc. Design Automat. Conf., June 1998, pp. 489-494.
    • (1998) Proc. Design Automat. Conf. , pp. 489-494
    • Wei, L.1    Chen, Z.2    Johnson, M.3    Roy, K.4    De, V.5
  • 3
    • 0032680122 scopus 로고    scopus 로고
    • Models and algorithms for bounds on leakage in CMOS circuits
    • June
    • M. C. Johnson, D. Somasekhar, and K. Roy, "Models and algorithms for bounds on leakage in CMOS circuits," IEEE Trans. on Computer-Aided Design, vol. 18, no. 6, pp. 714-725, June 1999.
    • (1999) IEEE Trans. on Computer-aided Design , vol.18 , Issue.6 , pp. 714-725
    • Johnson, M.C.1    Somasekhar, D.2    Roy, K.3
  • 4
  • 7
    • 1342281419 scopus 로고    scopus 로고
    • Low-power design using multiple channel lengths and oxide thicknesses
    • Jan.-Feb.
    • N. Sirisantana and K. Roy, "Low-power design using multiple channel lengths and oxide thicknesses," IEEE Design & Test of Computers, vol. 21, no. 1, pp. 56-63, Jan.-Feb. 2004.
    • (2004) IEEE Design & Test of Computers , vol.21 , Issue.1 , pp. 56-63
    • Sirisantana, N.1    Roy, K.2
  • 8
    • 0035694264 scopus 로고    scopus 로고
    • Impact of gate direct tunneling current on circuit performance: A simulation study
    • Dec.
    • C.-H. Choi, K.-Y. Nam, Z. Yu, and R. W. Dutton, "Impact of gate direct tunneling current on circuit performance: a simulation study," IEEE Trans. on Electron Devices, vol. 48, no. 12, pp. 2823-2329, Dec. 2001.
    • (2001) IEEE Trans. on Electron Devices , vol.48 , Issue.12 , pp. 2823-12329
    • Choi, C.-H.1    Nam, K.-Y.2    Yu, Z.3    Dutton, R.W.4
  • 9
    • 33748610684 scopus 로고    scopus 로고
    • Nanoscale Integration and Modeling Group, "45nm BSIM4 model cards," http://www.eas.asu.edu/~ptm/.
    • 45nm BSIM4 Model Cards


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.