-
1
-
-
3843068759
-
Methods for true energy-performance optimization
-
Aug
-
D. Markovic, V. Stojanovic, B. Nikolic, M. A. Horowitz, and R. W. Brodersen. Methods for true energy-performance optimization. IEEE J. of Solid-State Circuits, 39(8):1282-1293, Aug 2004.
-
(2004)
IEEE J. of Solid-State Circuits
, vol.39
, Issue.8
, pp. 1282-1293
-
-
Markovic, D.1
Stojanovic, V.2
Nikolic, B.3
Horowitz, M.A.4
Brodersen, R.W.5
-
2
-
-
0041633858
-
Parameter variation and impact on circuits and microarchitecture
-
June
-
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De. Parameter variation and impact on circuits and microarchitecture. In Proc. IEEE/ACM Design Automation Conf., pages 338-342, June 2003.
-
(2003)
Proc. IEEE/ACM Design Automation Conf
, pp. 338-342
-
-
Borkar, S.1
Karnik, T.2
Narendra, S.3
Tschanz, J.4
Keshavarzi, A.5
De, V.6
-
3
-
-
27944476890
-
Circuit optimization using statistical static timing analysis
-
June
-
A. Agarwal, K. Chopra, D. Blaauw, and V. Zolotov. Circuit optimization using statistical static timing analysis. In Proc. IEEE/ACM DAC, pages 321-324, June 2005.
-
(2005)
Proc. IEEE/ACM DAC
, pp. 321-324
-
-
Agarwal, A.1
Chopra, K.2
Blaauw, D.3
Zolotov, V.4
-
4
-
-
33751408241
-
Gate sizing using incremental parameterized statistical timing analysis
-
November
-
M. R. Guthaus, N. Venkateswaran, C. Visweswariah, and V. Zolotov. Gate sizing using incremental parameterized statistical timing analysis. In Proc. IEEE/ACM ICCAD, pages 1029-1036, November 2005.
-
(2005)
Proc. IEEE/ACM ICCAD
, pp. 1029-1036
-
-
Guthaus, M.R.1
Venkateswaran, N.2
Visweswariah, C.3
Zolotov, V.4
-
5
-
-
33751414776
-
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation
-
November
-
K. Chopra, S. Shah, A. Srivastava, D. Blaauw, and D. Sylvester. Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. In Proc. IEEE/ACM Int. Conf. on CAD, pages 1023-1028, November 2005.
-
(2005)
Proc. IEEE/ACM Int. Conf. on CAD
, pp. 1023-1028
-
-
Chopra, K.1
Shah, S.2
Srivastava, A.3
Blaauw, D.4
Sylvester, D.5
-
6
-
-
27944492787
-
Robust gate sizing by geometric programming
-
June
-
J. Singh, V. Nookala, Z. Luo, and S. Sapatnekar. Robust gate sizing by geometric programming. In Proc. IEEE/ACM Design Automation Conf., pages 315-320, June 2005.
-
(2005)
Proc. IEEE/ACM Design Automation Conf
, pp. 315-320
-
-
Singh, J.1
Nookala, V.2
Luo, Z.3
Sapatnekar, S.4
-
7
-
-
27944441297
-
An efficient algorithm for statistical minimization of total power under timing yield constraints
-
June
-
M. Mani, A. Devgan, and M. Orshansky. An efficient algorithm for statistical minimization of total power under timing yield constraints. In Proc. IEEE/ACM DAC, pages 309-314, June 2005.
-
(2005)
Proc. IEEE/ACM DAC
, pp. 309-314
-
-
Mani, M.1
Devgan, A.2
Orshansky, M.3
-
8
-
-
4444233012
-
First-order incremental block-based statistical timing analysis
-
June
-
C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, and S. Narayan. First-order incremental block-based statistical timing analysis. In Proc. IEEE/ACM DAC, June 2004.
-
(2004)
Proc. IEEE/ACM DAC
-
-
Visweswariah, C.1
Ravindran, K.2
Kalafala, K.3
Walker, S.4
Narayan, S.5
-
9
-
-
0346778721
-
Statistical timing analysis considering spatial correlations using a single pert-like traversal
-
November
-
H. Chang and S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single pert-like traversal. In Proc. IEEE/ACM ICCAD, November 2003.
-
(2003)
Proc. IEEE/ACM ICCAD
-
-
Chang, H.1
Sapatnekar, S.2
-
10
-
-
27944470947
-
Full-chip analysis of leakage power under process variations including spatial correlations
-
June
-
H. Chang and S. Sapatnekar. Full-chip analysis of leakage power under process variations including spatial correlations. In Proc. IEEE/ACM DAC, June 2005.
-
(2005)
Proc. IEEE/ACM DAC
-
-
Chang, H.1
Sapatnekar, S.2
-
11
-
-
0033712799
-
New paradigm of predictive mosfet and interconnect modeling for early circuit design
-
Y. Cao et al. New paradigm of predictive mosfet and interconnect modeling for early circuit design. In Proc. IEEE CICC, pages 201-204, 2000.
-
(2000)
Proc. IEEE CICC
, pp. 201-204
-
-
Cao, Y.1
-
12
-
-
0022231945
-
Tilos: A posynomial programming approach to transistor sizing
-
November
-
J. Fishburn and A. Dunlop. Tilos: a posynomial programming approach to transistor sizing. In Proc. IEEE/ACM ICCAD., pages 326-328, November 1985.
-
(1985)
Proc. IEEE/ACM ICCAD
, pp. 326-328
-
-
Fishburn, J.1
Dunlop, A.2
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