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Volumn , Issue , 2006, Pages 5603-5606

A novel low-power physical design methodology for MTCMOS

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER TRANSMISSION NETWORKS; LOGIC DESIGN; OPTIMIZATION; TRANSISTORS; VIRTUAL REALITY;

EID: 34547299425     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (13)
  • 1
    • 0036375848 scopus 로고    scopus 로고
    • Leakage Current in Low Standby Power and High Performance Devices: Trends and Challenges
    • San Diego, CA, Apr. 7-10
    • Geoffrey C-F Yeap, "Leakage Current in Low Standby Power and High Performance Devices: Trends and Challenges," In Proc. International Symposiums, on Physical Design, San Diego, CA, Apr. 7-10, 2002, pp.22-27.
    • (2002) Proc. International Symposiums, on Physical Design , pp. 22-27
    • Yeap, G.C.-F.1
  • 2
    • 0036911849 scopus 로고    scopus 로고
    • Sub-90nm Technologies - challenges and opportunities for CAD
    • San Jose, CA, Nov. 10-14
    • Karnik, T., Borkar, S., De, V., "Sub-90nm Technologies - challenges and opportunities for CAD," In Proc. the IEEE Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 10-14, 2002, pp.203-206.
    • (2002) Proc. the IEEE Int. Conf. Computer-Aided Design , pp. 203-206
    • Karnik, T.1    Borkar, S.2    De, V.3
  • 3
    • 34547334766 scopus 로고    scopus 로고
    • Design Optimization Methodologies for Low-Leakage Power Designs in Sub-90nm Technology
    • Kaijian Shi, Jason Binney, "Design Optimization Methodologies for Low-Leakage Power Designs in Sub-90nm Technology," Euro Design Con 2004
    • (2004) Euro Design Con
    • Shi, K.1    Binney, J.2
  • 5
    • 0036049095 scopus 로고    scopus 로고
    • Dynamic and Leakage Power Reduction in MTCMOS Circuits, Using an Automated Efficient Gate Clustering Technique
    • New Orleans, LA, Jun
    • Anis, M., Areibi, S., Mahmoud, M., Elmasry, M., "Dynamic and Leakage Power Reduction in MTCMOS Circuits, Using an Automated Efficient Gate Clustering Technique," In Proc. ACM/IEEE Design Automation Conference, New Orleans, LA, Jun, 10-14, 2002 pp. 480-485.
    • (2002) Proc. ACM/IEEE Design Automation Conference
    • Anis, M.1    Areibi, S.2    Mahmoud, M.3    Elmasry, M.4
  • 6
    • 0031639695 scopus 로고    scopus 로고
    • MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns
    • San Francisco, CA
    • Kao, J., Narendra, S., Chandrakasan, A., "MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns," In Proc. ACM/IEEE Design Automation Conference, San Francisco, CA 1998, pp.495-500.
    • (1998) Proc. ACM/IEEE Design Automation Conference , pp. 495-500
    • Kao, J.1    Narendra, S.2    Chandrakasan, A.3
  • 7
    • 16244414309 scopus 로고    scopus 로고
    • Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors
    • San Jose, CA Nov. 7-11
    • Khandelwal, V., Srivastava, A., "Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors," In Proc. the IEEE Int. Conf. Computer-Aided. Design, San Jose, CA Nov. 7-11, 2004, pp.533-536.
    • (2004) Proc. the IEEE Int. Conf. Computer-Aided. Design , pp. 533-536
    • Khandelwal, V.1    Srivastava, A.2
  • 8
    • 4544372894 scopus 로고    scopus 로고
    • Distributed Sleep Transistor Network for Power Reduction
    • Sept
    • Long, C., He, L., "Distributed Sleep Transistor Network for Power Reduction,"IEEE Trans on VLSI, Sept. 2004, 12(9): 937-946.
    • (2004) IEEE Trans on VLSI , vol.12 , Issue.9 , pp. 937-946
    • Long, C.1    He, L.2
  • 9
    • 0030697754 scopus 로고    scopus 로고
    • Kao, J., Chandrakasan, A., Antoniadis, D., Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology, In Proc. ACM/IEEE Design. Automation Conference, Anaheim, CA, Jun.9-11, 1997, pp.409-414.
    • Kao, J., Chandrakasan, A., Antoniadis, D., "Transistor Sizing Issues and Tool for Multi-Threshold CMOS Technology," In Proc. ACM/IEEE Design. Automation Conference, Anaheim, CA, Jun.9-11, 1997, pp.409-414.
  • 10
    • 0142118150 scopus 로고    scopus 로고
    • Design and Optimization of Multithreshold CMOS (MTCMOS) Circuits
    • Oct
    • Anis, M., Areibi, S., Elmasry, M., "Design and Optimization of Multithreshold CMOS (MTCMOS) Circuits," IEEE Trans on CAD, Oct. 2003, 22(10): 1324-1341.
    • (2003) IEEE Trans on CAD , vol.22 , Issue.10 , pp. 1324-1341
    • Anis, M.1    Areibi, S.2    Elmasry, M.3
  • 11
    • 1542329520 scopus 로고    scopus 로고
    • Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures, In Proc. the International Symposiums on Low Power Electronics and Design, Seoul, Korea, Aug. 25-27, 2003, pp. 22-25.
    • Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, "Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures," In Proc. the International Symposiums on Low Power Electronics and Design, Seoul, Korea, Aug. 25-27, 2003, pp. 22-25.
  • 13
    • 0026131224 scopus 로고
    • GORDIAN: VLSI placement by quadratic programming and slicing optimization
    • Mar
    • J. M. Kleinhans, G. Sigl, F. M. Johannes and K. J. Antreich, "GORDIAN: VLSI placement by quadratic programming and slicing optimization," IEEE Trans on CAD, Mar. 1991, 10(3):356-3.
    • (1991) IEEE Trans on CAD , vol.10 , Issue.3 , pp. 356-353
    • Kleinhans, J.M.1    Sigl, G.2    Johannes, F.M.3    Antreich, K.J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.