Managing standby and active mode leakage power in deep sub-micron design

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 274-279

  Clark, Lawrence T ^a   Patel, Rakesh ^b   Beatty, Timothy S ^b  

^a University of New Mexico   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Battery lifetime; Drowsy mode; MTCMOS; SRAM leakage control; TGSRAM; Thick gate shadow latch; Transistor leakage

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC BATTERIES; HAND HELD COMPUTERS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; STANDBY POWER SYSTEMS; STATIC RANDOM ACCESS STORAGE;

BATTERY LIFETIME; DROWSY MODE; LEAKAGE CONTROL; MTCMOS; TGSRAM; THICK GATE SHADOW LATCH; TRANSISTOR LEAKAGE;

LEAKAGE CURRENTS;

EID: 16244390532     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013239     Document Type: Conference Paper

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