A timing-driven algorithm for leakage reduction in MTCMOS FPGAs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2007, Pages 678-683

  Hassan, Hassan ^a   Anis, Mohab ^a   Elmasry, Mohamed ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

(E ,3E) PROCESS; APPLIED (CO); AVERAGE LEAKAGE; CIRCUIT TIMING; CMOS TECHNOLOGIES; DESIGN AUTOMATION CONFERENCE (DAC); FPGA ARCHITECTURES; LEAKAGE REDUCTION; PATH DELAY (PD); SLEEP TRANSISTORS; SOUTH PACIFIC; SUBTHRESHOLD LEAKAGE POWER; TIMING DRIVEN;

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENTS; INDUSTRIAL ENGINEERING; LEAKAGE CURRENTS; MECHANIZATION; TECHNOLOGY; TIME MEASUREMENT; TIMING CIRCUITS; TRANSISTORS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 46649120525     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2007.358065     Document Type: Conference Paper

References (15)

1. F. Li et al., "Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics," in Proc. of ISFPGA, 2004, pp. 42-50.
2. A. Gayasen et al., "Reducing Leakage Energy in FPGAs Using Region-Constrianed Placement," in Proc. of ISFPGA, 2004, pp. 51-58.
3. J. Anderson et al., "Active Leakage Power Optimization for FPGAs," in Proc. of ISFPGA, 2004, pp. 33-41.
4. A. Rahman et al., "Evaluation of Low-Leakage Design Techniques for Field Programmable Gate Arrays," in Proc. of ISFPGA, 2004, pp. 23-30.
5. H. Hassan et al., "LAP: A Logic Activity Packing Methodology for Leakage Power-Tolerant FPGAs," in Proc. of ISLPED, 2005, pp. 257-262.
6. T. Tuan et al., "A 90nm Low-Power FPGA for Battery-Powered Appliations," in Proc. of ISFPGA, 2006, pp. 3-11.
7. S. Mutoh et al., "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug 1995.
8. A. Marquardt et al., "Timing-driven placement for FPGAs," in Proc. of ISFPGA, 2000, pp. 203-213.
9. B. Calhoun et al., "A Leakage Reduction Methodology for Distributed MTCMOS," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 818-826, May 2004.
10. Z. Hu et al., "Microarchitectural Techniques for Power Gating of Execution Units," in Proc. of ISLPED, 2004, pp. 32-37.
11. M. Anis et al., "Design and Optimization of Multithreshold CMOS (MTCMOS) Circuits," IEEE Trans. Computer-Aided Design, vol. 22, no. 10, pp. 1324-1342, October 2003.
12. A. Marquardt et al., "Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density," in Proc. of ISFPGA, 1999, pp. 37-46.
13. K. Poon et al., "A Flexible Power Model for FPGAs," in Proc. of Intl. Conf. FPGAs, 2002, pp. 312-321.
14. F. Najm, "Transition Density, a Stochastic Measure of Activity in Digital Circuits," in Proc. of DAC, 1991, pp. 644-649.
15. The Berkeley Predictive Technology Model website. [Online]. Available: http://www-device.eecs.berkeley.edu/~ptm/