LECTOR: A Technique for Leakage Reduction in CMOS Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 2, 2004, Pages 196-205

  Hanchate, Narender ^a   Ranganathan, Nagarajan ^a  

^a University of South Florida   (United States)

Author keywords

Deep submicron; Leakage power; Power optimization; Transistor stacking

Indexed keywords

BENCHMARKING; CAPACITANCE; LEAKAGE CURRENTS; LOGIC GATES; OPTIMIZATION; SHORT CIRCUIT CURRENTS; SWITCHING CIRCUITS; THRESHOLD VOLTAGE; TRANSISTORS; VLSI CIRCUITS;

DEEP SUBMICRON; LEAKAGE POWER; POWER OPTIMIZATION; TRANSISTOR STACKING;

CMOS INTEGRATED CIRCUITS;

EID: 1642360827     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.821547     Document Type: Conference Paper

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