Low-power fanout optimization using MTCMOS and multi-Vt techniques

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2006, Issue , 2006, Pages 334-337

  Amelifard, Behnam ^a   Fallah, Farzan ^b   Pedarm, Massoud ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

Buffer chain; Fanout optimization; Fanout tree; Low power design

Indexed keywords

BUFFER CHAIN; FANOUT OPTIMIZATION; FANOUT TREE; LOW-POWER DESIGN;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; MATHEMATICAL MODELS; OPTIMIZATION;

DIGITAL INTEGRATED CIRCUITS;

EID: 34247202037     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1165573.1165652     Document Type: Conference Paper

References (14)

1. Salek, A., et al. Hierarchical buffered routing tree generation. IEEE Trans. on CAD, 21, (May 2002), 554-567.
2. Rezvani, P., et al. A fanout optimization algorithm based on the effort delay model. IEEE Trans. on CAD, 22, (Dec. 2003), 1671-1677.
3. Zhou, D., Liu, X. Minimization of chip size and power consumption of high-speed VLSI buffers. In Proc. ISPD, 1997, 186-191.
4. Singh, K. J., et al. A heuristic algorithm for the fanout problem. In Proc. DAC, 1990, 357-360.
5. Amelifard, B., et al., Low-power fanout optimization using multiple threshold voltage inverters. In Proc. ISLPED, 2005, 95-98.
6. Kung, D. S. A fast fanout optimization algorithm for near-continuous buffer libraries. In Proc. DAC., 1998, 352-355.
7. Sutherland, I., et al. Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, San Fransisco, CA, 1999.
8. Sakurai, T., et al. A simple MOSFET model for circuit analysis. IEEE Trans. Electron Device, 38 (Apr. 1991), 887-894.
9. De, V., et al. Techniques for leakage power reduction, in Design off High-Performance Microprocessor Circuit, Circuits, Chandrakasan, A.,et al., IEEE, Piscataway, NJ, 2001.
10. Pedram, M. Power minimization in IC design: Principles and applications. ACM Trans. on Design Automation of Electronic Systems, 1, 1 (Jan. 1996), 3-56.
11. Gill, P. E., et al. Practical Optimization, Academic Press, New York, 1981.
12. Anis, M., et al. Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering Technique. In Proc. DAC, 2002, 480-485.
13. Usami, K., et al. Automated selective multi-threshold design for ultra-low standby applications. In Proc. ISLPED, 2002, 202-206.
14. http://www.eas.asu.edu/~ptm/